sdk-nrf/applications/hpf/mspi/boards/nrf54lv10dk_nrf54lv10a_cpuflpr.overlay at 23e2517d6de61d3ce7378b8f8bd0f2cc0df3fcc5 · nrfconnect/sdk-nrf · GitHub

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/*
 * Copyright (c) 2024 Nordic Semiconductor ASA
 *
 * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
 */

/ {
	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;

		sram_tx: memory@2002b000 {
			reg = <0x2002b000 0x07f0>;
		};

		sram_rx: memory@2002b7f0 {
			reg = <0x2002b7f0 0x07f0>;
		};

		cpuflpr_error_code: memory@2002bfe0 {
			reg = <0x2002bfe0 0x0020>; /* 32 bytes */
		};
	};

	ipc {
		ipc0: ipc0 {
			compatible = "zephyr,ipc-icmsg";
			tx-region = <&sram_tx>;
			rx-region = <&sram_rx>;
			mboxes = <&cpuflpr_vevif_rx 16>, <&cpuflpr_vevif_tx 20>;
			mbox-names = "rx", "tx";
			status = "okay";
		};
	};
};

&cpuflpr_rram {
	reg = <0xf9400 DT_SIZE_K(15)>;
	ranges = <0x0 0xf9400 DT_SIZE_K(15)>;
};

&cpuflpr_code_partition {
	reg = <0x0 DT_SIZE_K(15)>;
};

&cpuflpr_sram {
	reg = <0x2002c000 DT_SIZE_K(15)>;
	ranges = <0x0 0x2002c000 0x3c00>;
};

&cpuflpr_vevif_rx {
	status = "okay";
	interrupts = <16 NRF_DEFAULT_IRQ_PRIORITY>;
	nordic,tasks = <1>;
	nordic,tasks-mask = <0x00010000>;
};

&cpuflpr_vevif_tx {
	status = "okay";
};

&gpio0 {
	status = "disabled";
};

&gpio1 {
	status = "disabled";
};

&gpiote20 {
	status = "disabled";
};

&gpiote30 {
	status = "disabled";
};

&grtc {
	status = "disabled";
};

&uart20 {
	status = "disabled";
};

&uart30 {
	status = "disabled";
};