applications: nrf_desktop: nrf54lm20dk: increase USB HS report rate

Updated the nRF54LM20 DK configuration in the nRF Desktop application
to increase the USB High Speed performance by executing application
code from RAM. Due to this change, the application can now consistently
maintain the 8000Hz report rate in the mouse release configuration.

To execute code from RAM, the MCUboot mode has been changed from the
direct-xip mode to the RAM load mode. The bootloader now copies the
newer application image from one of two RRAM slots into the RAM
region and then it starts the application from RAM.

To support RAM load mode of the MCUboot bootloader, the partitioning
method has been changed from the Partition Manager (PM) to devicetree
(DTS). Currently, the PM is not properly supported in the RAM load
mode.

Ref: NCSDK-35506

Signed-off-by: Aleksander Strzebonski <[email protected]>
Signed-off-by: Kamil Piszczek <[email protected]>

Author: kapi-no

applications/nrf_desktop/configuration/nrf54lm20dk_nrf54lm20a_cpuapp/app_common.dtsi

@@ -4,12 +4,16 @@
  * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
  */
 
-/* Application does not use cpuflpr core. Assign whole RRAM to cpuapp. */
-&cpuapp_rram {
-	reg = < 0x0 DT_SIZE_K(2036) >;
-};
+#include "memory_map.dtsi"
 
 / {
+	chosen {
+		/* We need to point where we want to place the retained memory region that
+		 * is shared with the application image and contains the image metadata.
+		 */
+		zephyr,bootloader-info = &boot_info0;
+	};
+
 	/* Disable pwmleds and redefine them to align configuration with CAF LEDs requirements. */
 	/delete-node/ pwmleds;
 

applications/nrf_desktop/configuration/nrf54lm20dk_nrf54lm20a_cpuapp/images/mcuboot/app.overlay

@@ -4,7 +4,17 @@
  * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
  */
 
-/* Application does not use cpuflpr core. Assign whole RRAM to cpuapp. */
-&cpuapp_rram {
-	reg = < 0x0 DT_SIZE_K(2036) >;
+#include "../../memory_map.dtsi"
+
+/ {
+	chosen {
+		/* We need to point where we want to place MCUboot code. */
+		zephyr,code-partition = &boot_partition;
+		/* We need to point where we want to place MCUboot RAM region. */
+		zephyr,sram = &cpuapp_sram_mcuboot_ram_region;
+		/* We need to point where we want to place the retained memory region that
+		 * is shared with the application image and contains the image metadata.
+		 */
+		zephyr,bootloader-info = &boot_info0;
+	};
 };

applications/nrf_desktop/configuration/nrf54lm20dk_nrf54lm20a_cpuapp/images/mcuboot/prj.conf

@@ -15,6 +15,14 @@ CONFIG_BOOT_VERSION_CMP_USE_BUILD_NUMBER=y
 
 CONFIG_FLASH=y
 
+# Enable retained memory and retention to support the MCUboot RAM load mode.
+CONFIG_RETAINED_MEM=y
+CONFIG_RETENTION=y
+CONFIG_RETAINED_MEM_ZEPHYR_RAM=y
+CONFIG_BOOT_SHARE_DATA=y
+CONFIG_BOOT_SHARE_DATA_BOOTINFO=y
+CONFIG_BOOT_SHARE_BACKEND_RETENTION=y
+
 # Reduce memory consumption
 CONFIG_BOOT_BANNER=n
 CONFIG_NCS_BOOT_BANNER=n
@@ -36,3 +44,7 @@ CONFIG_ISR_TABLES_LOCAL_DECLARATION=y
 
 # Improve debugging experience by disabling reset on fatal error
 CONFIG_RESET_ON_FATAL_ERROR=n
+
+# Set according to the configuration of the cpuapp_sram_app_rxm_region DTS node.
+CONFIG_BOOT_IMAGE_EXECUTABLE_RAM_START=0x20000000
+CONFIG_BOOT_IMAGE_EXECUTABLE_RAM_SIZE=517120

applications/nrf_desktop/configuration/nrf54lm20dk_nrf54lm20a_cpuapp/images/mcuboot/prj_llvm.conf

@@ -15,6 +15,14 @@ CONFIG_BOOT_VERSION_CMP_USE_BUILD_NUMBER=y
 
 CONFIG_FLASH=y
 
+# Enable retained memory and retention to support the MCUboot RAM load mode.
+CONFIG_RETAINED_MEM=y
+CONFIG_RETENTION=y
+CONFIG_RETAINED_MEM_ZEPHYR_RAM=y
+CONFIG_BOOT_SHARE_DATA=y
+CONFIG_BOOT_SHARE_DATA_BOOTINFO=y
+CONFIG_BOOT_SHARE_BACKEND_RETENTION=y
+
 # Reduce memory consumption
 CONFIG_BOOT_BANNER=n
 CONFIG_NCS_BOOT_BANNER=n
@@ -36,3 +44,7 @@ CONFIG_ISR_TABLES_LOCAL_DECLARATION=n
 
 # Improve debugging experience by disabling reset on fatal error
 CONFIG_RESET_ON_FATAL_ERROR=n
+
+# Set according to the configuration of the cpuapp_sram_app_rxm_region DTS node.
+CONFIG_BOOT_IMAGE_EXECUTABLE_RAM_START=0x20000000
+CONFIG_BOOT_IMAGE_EXECUTABLE_RAM_SIZE=517120

applications/nrf_desktop/configuration/nrf54lm20dk_nrf54lm20a_cpuapp/images/mcuboot/prj_release.conf

@@ -16,6 +16,14 @@ CONFIG_BOOT_VERSION_CMP_USE_BUILD_NUMBER=y
 
 CONFIG_FLASH=y
 
+# Enable retained memory and retention to support the MCUboot RAM load mode.
+CONFIG_RETAINED_MEM=y
+CONFIG_RETENTION=y
+CONFIG_RETAINED_MEM_ZEPHYR_RAM=y
+CONFIG_BOOT_SHARE_DATA=y
+CONFIG_BOOT_SHARE_DATA_BOOTINFO=y
+CONFIG_BOOT_SHARE_BACKEND_RETENTION=y
+
 CONFIG_RESET_ON_FATAL_ERROR=y
 
 # Reduce memory consumption
@@ -36,3 +44,7 @@ CONFIG_USE_SEGGER_RTT=n
 # Activate Link Time Optimization (LTO)
 CONFIG_LTO=y
 CONFIG_ISR_TABLES_LOCAL_DECLARATION=y
+
+# Set according to the configuration of the cpuapp_sram_app_rxm_region DTS node.
+CONFIG_BOOT_IMAGE_EXECUTABLE_RAM_START=0x20000000
+CONFIG_BOOT_IMAGE_EXECUTABLE_RAM_SIZE=517120

applications/nrf_desktop/configuration/nrf54lm20dk_nrf54lm20a_cpuapp/memory_map.dtsi

@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+ */
+
+&cpuapp_rram {
+	/* Application does not use cpuflpr core. Assign whole RRAM to cpuapp. */
+	reg = < 0x0 DT_SIZE_K(2036) >;
+
+	/* Redefine the "partitions" DTS node. */
+	/delete-node/ partitions;
+
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/* Significantly increase the size of the MCUboot partition to make it fit
+		 * for the LLVM configuration variant.
+		 */
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0x0 DT_SIZE_K(48)>;
+		};
+
+		slot0_partition: partition@c000 {
+			label = "image-0";
+			reg = <0xc000 DT_SIZE_K(984)>;
+		};
+
+		slot1_partition: partition@102000 {
+			label = "image-1";
+			reg = <0x102000 DT_SIZE_K(984)>;
+		};
+
+		storage_partition: partition@1f8000 {
+			label = "storage";
+			reg = <0x1f8000 DT_SIZE_K(20)>;
+		};
+	};
+};
+
+/ {
+	soc {
+		/* Redefine the "cpuapp_sram" DTS node and specify the necessary RAM subregions
+		 * that can be used to configure the MCUboot image. This DTS node must be assigned
+		 * to the application image as its chosen SRAM DTS node. The build system places
+		 * the executable ROM section (code) at the beginning of this region and the RAM
+		 * section (data) right after the ROM section. The usage of this SRAM region should
+		 * not be close to the maximum size of this region (100%), as the System Heap is
+		 * located in the unused part of this region. It is recommended to have at least
+		 * 1kB of unused space.
+		 */
+		cpuapp_sram: memory@20000000 {
+			compatible = "mmio-sram";
+			reg = <0x20000000 DT_SIZE_K(510)>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x20000000 DT_SIZE_K(510)>;
+
+			/* SRAM region for storing the ROM section (code) and RAM section (data) of
+			 * the application image. The RAM section of the application image may also
+			 * partially or fully fill the subsequent SRAM region called
+			 * "cpuapp_sram_mcuboot_ram_region", but its ROM section must never fill
+			 * this region. It is recommended to use this DTS node for configuration
+			 * of the executable SRAM region in the MCUboot image. This RAM region
+			 * should be aligned with the following Kconfig options in MCUboot:
+			 * - CONFIG_BOOT_IMAGE_EXECUTABLE_RAM_START
+			 * - CONFIG_BOOT_IMAGE_EXECUTABLE_RAM_SIZE
+			 */
+			cpuapp_sram_app_rxm_region: memory@0 {
+				compatible = "mmio-sram";
+				reg = <0x0 DT_SIZE_K(490)>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0x0 DT_SIZE_K(490)>;
+			};
+
+			/* SRAM region for storing the RAM section (data) of the MCUboot image. The
+			 * RAM section of the application image may also partially or fully fill
+			 * this region, but the ROM section of the application image must never
+			 * fill this region. This DTS node must be assigned to the MCUboot image
+			 * as its chosen SRAM DTS node. The usage of this SRAM region should not
+			 * be close to the maximum size of this region (100%), as the System Heap
+			 * is located in the unused part of this region. It is recommended to have
+			 * at least 1kB of unused space.
+			 */
+			cpuapp_sram_mcuboot_ram_region: memory@7a800 {
+				compatible = "mmio-sram";
+				reg = <0x7a800 DT_SIZE_K(20)>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0x7a800 DT_SIZE_K(20)>;
+			};
+		};
+
+		/* SRAM region that is retained across reboots. This region is shared by both the
+		 * MCUboot image and the application code. Currently, it is used to share the image
+		 * metadata between the bootloader and the application.
+		 */
+		cpuapp_sram_retained_mem_region: memory@2007f800 {
+			compatible = "zephyr,memory-region", "mmio-sram";
+			reg = <0x2007f800 DT_SIZE_K(1)>;
+			zephyr,memory-region = "RetainedMem";
+			status = "okay";
+
+			retainedmem {
+				compatible = "zephyr,retained-ram";
+				status = "okay";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				boot_info0: boot_info@0 {
+					compatible = "zephyr,retention";
+					status = "okay";
+					reg = <0x0 0x100>;
+				};
+			};
+		};
+	};
+};