softperipheral: rev 7262e00b5f72fd04b8e0c9b92b743d907b9a106b

Using new naming convention: nrfx_qspi2 -> nrf_sqspi
Using sQSPI 0.2.0 firmware (which now uses PIC)
Deleting old driver files

Signed-off-by: Luis David Lopez <[email protected]>

IP-10301: Cosmetic fixes

Author: lopeztel

softperipheral/CHANGELOG.rst

@@ -20,3 +20,15 @@ See the following list of changes:
 
   * The first implementation of Soft Peripheral sQSPI for the nRF54L15 and nRF54H20 SoCs.
     For details, see the :ref:`sqspi_changelog` page.
+
+nRF Connect SDK v3.1.0
+**********************
+
+This is a release that focuses on improving existing soft peripherals.
+See the following list of changes:
+
+
+* Bug fixes:
+
+  * Fixed higher frequency transfers for Soft Peripheral sQSPI for the nRF54L15 and nRF54H20 SoCs.
+    For details, see the :ref:`sqspi_changelog` page.

softperipheral/doc/sQSPI/CHANGELOG.rst

@@ -20,3 +20,15 @@ This is an initial release.
   * Configurable :ref:`clock phase and polarity<sqspi_features_clock_phase>`.
   * :ref:`Delayed read sampling <sqspi_features_read_sampling>`.
   * Support for :ref:`various packet formats <sqspi_features_packet_formats>`.
+
+v0.2.0
+******
+
+This is an improvement release.
+
+* Added the following for nRF54L15 devices:
+
+  * Support for preparing (holding) transfers.
+  * Higher speed transfers are now supported (>=33 MHz) by using GPIOHSPADCTL.
+  * Position Independent Code for more flexibility when placing the firmware.
+  * Initial support to use with displays.

softperipheral/include/softperipheral_meta.h

@@ -9,8 +9,6 @@
 
 #include <stdint.h>
 
-#define SOFTPERIPHERAL_META_HEADER_VERSION          (1)
-
 #define SOFTPERIPHERAL_META_SOFTPERIPHERAL_ID_SQSPI 0x45b1
 
 #if (SOFTPERIPHERAL_META_HEADER_VERSION == 1)
@@ -124,6 +122,111 @@ typedef struct
     };
 } softperipheral_metadata_t;
 
-#endif // (SOFTPERIPHERAL_META_HEADER_VERSION == 1)
+#elif  (SOFTPERIPHERAL_META_HEADER_VERSION == 2)
+
+#define SOFTPERIPHERAL_META_COMM_ID_REGIF         (1)
+#define SOFTPERIPHERAL_META_COMM_ID_JOBLIST       (2)
+
+#define SOFTPERIPHERAL_META_PLATFORM_DEVICE_05    (1)
+#define SOFTPERIPHERAL_META_PLATFORM_DEVICE_09    (2)
+#define SOFTPERIPHERAL_META_PLATFORM_DEVICE_10    (4)
+#define SOFTPERIPHERAL_META_PLATFORM_DEVICE_15    (8)
+#define SOFTPERIPHERAL_META_PLATFORM_DEVICE_20    (16)
+#define SOFTPERIPHERAL_META_PLATFORM_DEVICE_ANY   (31)
+
+#define SOFTPERIPHERAL_META_PLATFORM_PLATFORM_L   (1)
+#define SOFTPERIPHERAL_META_PLATFORM_PLATFORM_H   (2)
+#define SOFTPERIPHERAL_META_PLATFORM_PLATFORM_ANY (3)
+
+#define SOFTPERIPHERAL_META_PLATFORM_SERIES_54    (1)
+#define SOFTPERIPHERAL_META_PLATFORM_SERIES_ANY   (1)
+
+#ifndef SOFTPERIPHERAL_META_SELF_BOOTING
+#define SOFTPERIPHERAL_META_SELF_BOOTING (0)
+#endif
+
+typedef struct
+{
+    union
+    {
+        struct
+        {
+            uint32_t magic          : 16;
+            uint32_t header_version : 4;
+            uint32_t comm_id        : 8;
+            uint32_t reserved0      : 3;
+            uint32_t self_boot      : 1; // If True, set INITPC to NVM address.
+                                         // If False, copy fw_code_size bytes from NVM to fw_ram_base_addr
+        };
+
+        uint32_t w0_raw;
+    };
+
+    union
+    {
+        struct
+        {
+            uint16_t softperiph_id;
+
+            union
+            {
+                struct
+                {
+                    uint16_t device   : 9;
+                    uint16_t platform : 4;
+                    uint16_t series   : 3;
+                };
+
+                uint16_t raw;
+            }        platform;
+        };
+
+        uint32_t w1_raw;
+    };
+
+    union
+    {
+        struct
+        {
+            uint32_t patch : 16;
+            uint32_t minor : 8;
+            uint32_t major : 8;
+        }        version;
+
+        uint32_t w2_raw;
+    };
+
+    union
+    {
+        struct
+        {
+            uint16_t fw_code_size;      // size / 16
+            uint16_t
+                     fw_ram_total_size; // size / 16. Must also include code (RAM CODE region), code RAM (.data/.bss/.stack/.heap), shared and/or allocatable RAM from the FW.
+        };
+
+        uint32_t w3_raw;
+    };
+
+    union
+    {
+        uint32_t
+                 fw_ram_base_addr; // Dest address for code in case self_boot = False. Also, the RAM start address set by the FW in case of any RAM it needs.
+        uint32_t w5_raw;
+    };
+
+    union
+    {
+        struct
+        {
+            uint16_t fw_shared_ram_size; // size / 16
+            uint16_t fw_shared_ram_addr_offset;
+        };
+
+        uint32_t w6_raw;
+    };
+} softperipheral_metadata_t;
+
+#endif //SOFTPERIPHERAL_META_HEADER_VERSION
 
 #endif // SOFTPERIPHEREAL_META_H__

softperipheral/include/softperipheral_regif.h

@@ -8,7 +8,8 @@
 #define SOFTPERIPHERAL_REGIF_H__
 
 /* Shared between Host and Service, varies between platforms. */
-#if defined(NRF54L15_XXAA)
+#if defined (NRF54L05_XXAA) || defined (NRF54L09_ENGA_XXAA) || defined (NRF54L10_XXAA) || \
+    defined (NRF54L15_XXAA) || defined (NRF54L20_ENGA_XXAA) || defined (NRF54LM20A_ENGA_XXAA)
 #define SP_VPR_EVENT_IDX                  20
 #define NRF_VPR                           NRF_VPR00
 #define SP_VPR_TASK_DPPI_0_IDX            16 // Channel 0
@@ -46,7 +47,7 @@
     do {                                                                                   \
         nrf_qspi2_core_dr_x(R, m_task_count, 20);                                          \
         nrf_vpr_task_trigger(P, (nrf_vpr_task_t)offsetof(NRF_VPR_Type, TASKS_TRIGGER[T])); \
-        while (m_task_count != nrf_qspi2_core_dr_x_get(R, 21)) {                           \
+        while (nrf_qspi2_core_dr_x_get(R, 20) != nrf_qspi2_core_dr_x_get(R, 21)) {         \
            __NOP();                                                                        \
            __NOP();                                                                        \
            __NOP();                                                                        \

softperipheral/sQSPI/include/nrf54h20/sqspi_firmware.h

@@ -6,5 +6,6 @@
 
 #ifndef SQSPI_FIRMWARE_H__
 #define SQSPI_FIRMWARE_H__
-#include "sqspi_firmware_v0.1.0.h"
+#include "sqspi_firmware_v0.2.0.h"
+#define SOFTPERIPHERAL_META_HEADER_VERSION 2
 #endif