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softperipheral: rev cf28ddf86b89fb647ee876546770c2676b3bc63c
softperipheral/CHANGELOG.rst contains the list of changes. Signed-off-by: Luis David Lopez <[email protected]>
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‎.checkpatch.conf‎

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--exclude gzll
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--exclude nfc
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--exclude nrf_modem/include
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--exclude softperipheral

‎CODEOWNERS‎

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/lc3/ @koffes @alexsven
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/nrf_fuel_gauge/ @nordic-auko
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/nrf_wifi/ @udaynordic @rajb9 @srkanordic
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/softperipheral/ @lopeztel

‎README.rst‎

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openthread/README
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nrf_rpc/README
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softdevice_controller/README
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softperipheral/README

‎doc/links.txt‎

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.. _`nrfx`: https://github.com/NordicSemiconductor/nrfx/
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.. _`sdk-nrfxlib`: https://github.com/nrfconnect/sdk-nrfxlib
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.. _`TinyCBOR`: https://github.com/zephyrproject-rtos/tinycbor
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.. _`zcbor`: https://github.com/NordicSemiconductor/zcbor

‎softperipheral/README.rst‎

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.. _soft_peripherals:
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Soft peripherals
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################
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.. contents::
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:local:
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:depth: 2
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This documentation outlines the concept of soft peripherals, designed to emulate hardware peripherals using the Fast Lightweight Peripheral Processor (FLPR).
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It covers setup, integration, and operational guidelines for using each soft peripheral through the nrfx driver API, alongside detailed descriptions of limitations and performance considerations.

‎softperipheral/include/softperipheral_meta.h‎

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/*
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* Copyright (c) 2025 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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*/
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#ifndef SOFTPERIPHERAL_META_H__
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#define SOFTPERIPHERAL_META_H__
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#include <stdint.h>
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#define SOFTPERIPHERAL_META_HEADER_VERSION (1)
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#define SOFTPERIPHERAL_META_SOFTPERIPHERAL_ID_SQSPI 0x45b1
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#if (SOFTPERIPHERAL_META_HEADER_VERSION == 1)
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#define SOFTPERIPHERAL_META_COMM_ID_REGIF (1)
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#define SOFTPERIPHERAL_META_COMM_ID_JOBLIST (2)
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#define SOFTPERIPHERAL_META_PLATFORM_DEVICE_15 (15)
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#define SOFTPERIPHERAL_META_PLATFORM_DEVICE_20 (20)
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#define SOFTPERIPHERAL_META_PLATFORM_PLATFORM_L (0)
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#define SOFTPERIPHERAL_META_PLATFORM_PLATFORM_H (1)
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#define SOFTPERIPHERAL_META_PLATFORM_SERIES_54 (54)
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#ifndef SOFTPERIPHERAL_META_SELF_BOOTING
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#define SOFTPERIPHERAL_META_SELF_BOOTING (0)
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#endif
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typedef struct
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{
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union
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{
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struct
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{
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uint32_t magic : 16;
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uint32_t header_version : 4;
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uint32_t comm_id : 8;
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uint32_t reserved0 : 3;
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uint32_t self_boot : 1; // If True, set INITPC to NVM address.
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// If False, copy fw_code_size bytes from NVM to fw_ram_base_addr
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};
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uint32_t w0_raw;
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};
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union
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{
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struct
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{
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uint16_t softperiph_id;
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union
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{
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struct
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{
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uint16_t device : 7;
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uint16_t platform : 2;
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uint16_t series : 7;
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};
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uint16_t raw;
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} platform;
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};
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uint32_t w1_raw;
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};
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union
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{
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struct
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{
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uint32_t patch : 16;
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uint32_t minor : 8;
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uint32_t major : 8;
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} version;
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uint32_t w2_raw;
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};
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union
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{
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struct
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{
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uint16_t fw_code_size; // size / 16
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uint16_t
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fw_ram_total_size; // size / 16. Must also include code (RAM CODE region), code RAM (.data/.bss/.stack/.heap), shared and/or allocatable RAM from the FW.
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};
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uint32_t w3_raw;
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};
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union
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{
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uint32_t fw_code_addr; // Address of where the code is compiled to run from.
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uint32_t w4_raw;
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};
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union
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{
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uint32_t
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fw_ram_base_addr; // Dest address for code in case self_boot = False. Also, the RAM start address set by the FW in case of any RAM it needs.
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uint32_t w5_raw;
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};
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union
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{
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struct
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{
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uint16_t fw_shared_ram_size; // size / 16
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uint16_t fw_shared_ram_addr_offset;
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};
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uint32_t w6_raw;
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};
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union
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{
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uint32_t fw_vpr_save_ctx_addr;
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uint32_t w7_raw;
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};
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} softperipheral_metadata_t;
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#endif // (SOFTPERIPHERAL_META_HEADER_VERSION == 1)
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#endif // SOFTPERIPHEREAL_META_H__

‎softperipheral/include/softperipheral_regif.h‎

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/*
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* Copyright (c) 2025 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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*/
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#ifndef SOFTPERIPHERAL_REGIF_H__
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#define SOFTPERIPHERAL_REGIF_H__
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/* Shared between Host and Service, varies between platforms. */
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#if defined(NRF54L15_XXAA)
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#define SP_VPR_EVENT_IDX 20
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#define NRF_VPR NRF_VPR00
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#define SP_VPR_TASK_DPPI_0_IDX 16 // Channel 0
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#define SP_VPR_TASK_CONFIG_IDX 18
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#define SP_VPR_TASK_ACTION_IDX 19
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#define SP_VPR_TASK_STOP_IDX 21
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#define SP_VPR_TASK_PROTOCOL_SPECIFIC_IDX 22
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#define SP_VPR_IRQHandler VPR00_IRQHandler
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#define SP_VPR_IRQn VPR00_IRQn
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#define SP_VPR_BASE_FREQ_HZ 128000000
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#elif defined(NRF54H20_XXAA)
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#define SP_VPR_EVENT_IDX 28
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#define NRF_VPR NRF_VPR121
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#define SP_VPR_TASK_DPPI_0_IDX 24 // Channel 0
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#define SP_VPR_TASK_CONFIG_IDX 16
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#define SP_VPR_TASK_ACTION_IDX 17
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#define SP_VPR_TASK_STOP_IDX 22
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#define SP_VPR_TASK_PROTOCOL_SPECIFIC_IDX 23
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#define SP_VPR_IRQHandler VPR121_IRQHandler
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#define SP_VPR_IRQn VPR121_IRQn
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#define SP_VPR_BASE_FREQ_HZ 320000000
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#else
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#pragma warning "Processor not defined."
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#endif
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#if defined(NRF_APPLICATION)
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#ifndef SP_VPR_FIRMWARE_ADDRESS
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#define SP_VPR_FIRMWARE_ADDRESS 0x00040000
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#endif
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/* Config Synchronization Barrier (ASB). */
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#if 1
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#define __XSBx(R, P, T) \
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do { \
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nrf_qspi2_core_dr_x(R, m_task_count, 20); \
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nrf_vpr_task_trigger(P, (nrf_vpr_task_t)offsetof(NRF_VPR_Type, TASKS_TRIGGER[T])); \
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while (m_task_count != nrf_qspi2_core_dr_x_get(R, 21)) { \
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__NOP(); \
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__NOP(); \
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__NOP(); \
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} \
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m_task_count++; \
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} while (0);
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#else
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#define __XSBx(R, P, T) \
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do { \
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nrf_vpr_task_trigger(P, (nrf_vpr_task_t)offsetof(NRF_VPR_Type, TASKS_TRIGGER[T])); \
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} while (0);
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#endif
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#define __CSB(R) __XSBx(R, NRF_VPR, SP_VPR_TASK_CONFIG_IDX);
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#define __ASB(R) __XSBx(R, NRF_VPR, SP_VPR_TASK_ACTION_IDX);
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#define __SSB(R) __XSBx(R, NRF_VPR, SP_VPR_TASK_STOP_IDX);
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#define __PSB(R) __XSBx(R, NRF_VPR, SP_VPR_TASK_PROTOCOL_SPECIFIC_IDX);
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#endif
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#endif // SOFTPERIPHERAL_REGIF_H__

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