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imapaimapa
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nrf_wifi: Update RPU patch to rev#c96a720c9e4
[SHEL-3087]: Determine the Chip package and modify the optimized setting value for PALDOTRIM to 3.4V for CSP and leave it unchanged at 3.3V for QFN. [SHEL-2768]: Develop patch for Enhanced TX DC algorithm. Signed-off-by: Mahammadyunus Patil <[email protected]>
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7 files changed

+37
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‎nrf_wifi/fw_bins/default/nrf70.bin‎

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‎nrf_wifi/fw_bins/radio_test/nrf70.bin‎

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‎nrf_wifi/fw_bins/scan_only/nrf70.bin‎

2.07 KB
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‎nrf_wifi/fw_bins/system_with_raw/nrf70.bin‎

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‎nrf_wifi/fw_if/umac_if/inc/fw/lmac_if_common.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -21,8 +21,8 @@
2121
#define RPU_MEM_LMAC_BOOT_SIG 0xB7000D50
2222
#define RPU_MEM_LMAC_VER 0xB7000D54
2323

24-
#define RPU_MEM_LMAC_PATCH_BIN 0x80044000
25-
#define RPU_MEM_LMAC_PATCH_BIMG 0x8004B400
24+
#define RPU_MEM_LMAC_PATCH_BIN 0x80043A80
25+
#define RPU_MEM_LMAC_PATCH_BIMG 0x8004BC00
2626

2727
#define NRF_WIFI_LMAC_VER(ver) ((ver & 0xFF000000) >> 24)
2828
#define NRF_WIFI_LMAC_VER_MAJ(ver) ((ver & 0x00FF0000) >> 16)

‎nrf_wifi/fw_if/umac_if/src/fmac_api_common.c‎

Lines changed: 13 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -901,12 +901,6 @@ int nrf_wifi_phy_rf_params_init(struct nrf_wifi_phy_rf_params *prf,
901901
prf->pd_adjust_val.pd_adjt_hb_mid_chan = PD_ADJUST_VAL;
902902
prf->pd_adjust_val.pd_adjt_hb_high_chan = PD_ADJUST_VAL;
903903

904-
/* Configure systematic offset value */
905-
prf->syst_tx_pwr_offset.syst_off_lb_chan = SYSTEM_OFFSET_LB;
906-
prf->syst_tx_pwr_offset.syst_off_hb_low_chan = SYSTEM_OFFSET_HB_CHAN_LOW;
907-
prf->syst_tx_pwr_offset.syst_off_hb_mid_chan = SYSTEM_OFFSET_HB_CHAN_MID;
908-
prf->syst_tx_pwr_offset.syst_off_hb_high_chan = SYSTEM_OFFSET_HB_CHAN_HIGH;
909-
910904
/* RX Gain offsets */
911905
prf->rx_gain_offset.rx_gain_lb_chan = RX_GAIN_OFFSET_LB_CHAN;
912906
prf->rx_gain_offset.rx_gain_hb_low_chan = RX_GAIN_OFFSET_HB_LOW_CHAN;
@@ -915,6 +909,13 @@ int nrf_wifi_phy_rf_params_init(struct nrf_wifi_phy_rf_params *prf,
915909

916910
if (package_info == CSP_PACKAGE_INFO) {
917911
prf->xo_offset.xo_freq_offset = CSP_XO_VAL;
912+
913+
/* Configure systematic offset value */
914+
prf->syst_tx_pwr_offset.syst_off_lb_chan = CSP_SYSTEM_OFFSET_LB;
915+
prf->syst_tx_pwr_offset.syst_off_hb_low_chan = CSP_SYSTEM_OFFSET_HB_CHAN_LOW;
916+
prf->syst_tx_pwr_offset.syst_off_hb_mid_chan = CSP_SYSTEM_OFFSET_HB_CHAN_MID;
917+
prf->syst_tx_pwr_offset.syst_off_hb_high_chan = CSP_SYSTEM_OFFSET_HB_CHAN_HIGH;
918+
918919
/* TX power ceiling */
919920
prf->max_pwr_ceil.max_dsss_pwr = CSP_MAX_TX_PWR_DSSS;
920921
prf->max_pwr_ceil.max_lb_mcs7_pwr = CSP_MAX_TX_PWR_LB_MCS7;
@@ -949,6 +950,12 @@ int nrf_wifi_phy_rf_params_init(struct nrf_wifi_phy_rf_params *prf,
949950
/* Initialize XO */
950951
prf->xo_offset.xo_freq_offset = QFN_XO_VAL;
951952

953+
/* Configure systematic offset value */
954+
prf->syst_tx_pwr_offset.syst_off_lb_chan = QFN_SYSTEM_OFFSET_LB;
955+
prf->syst_tx_pwr_offset.syst_off_hb_low_chan = QFN_SYSTEM_OFFSET_HB_CHAN_LOW;
956+
prf->syst_tx_pwr_offset.syst_off_hb_mid_chan = QFN_SYSTEM_OFFSET_HB_CHAN_MID;
957+
prf->syst_tx_pwr_offset.syst_off_hb_high_chan = QFN_SYSTEM_OFFSET_HB_CHAN_HIGH;
958+
952959
/* TX power ceiling */
953960
prf->max_pwr_ceil.max_dsss_pwr = QFN_MAX_TX_PWR_DSSS;
954961
prf->max_pwr_ceil.max_lb_mcs7_pwr = QFN_MAX_TX_PWR_LB_MCS7;

‎nrf_wifi/hw_if/hal/inc/fw/phy_rf_params.h‎

Lines changed: 22 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -57,6 +57,7 @@
5757
/* Temperature based calibration params */
5858
#define NRF_WIFI_DEF_PHY_TEMP_CALIB (NRF_WIFI_PHY_CALIB_FLAG_RXDC |\
5959
NRF_WIFI_PHY_CALIB_FLAG_TXDC |\
60+
NRF_WIFI_PHY_CALIB_FLAG_ENHANCED_TXDC |\
6061
NRF_WIFI_PHY_CALIB_FLAG_RXIQ |\
6162
NRF_WIFI_PHY_CALIB_FLAG_TXIQ |\
6263
NRF_WIFI_PHY_CALIB_FLAG_TXPOW |\
@@ -88,11 +89,7 @@
8889
#define RX_GAIN_OFFSET_HB_MID_CHAN 0
8990
#define RX_GAIN_OFFSET_HB_HIGH_CHAN 0
9091

91-
/** Systematic error between set power and measured power in dBm */
92-
#define SYSTEM_OFFSET_LB 3
93-
#define SYSTEM_OFFSET_HB_CHAN_LOW 3
94-
#define SYSTEM_OFFSET_HB_CHAN_MID 3
95-
#define SYSTEM_OFFSET_HB_CHAN_HIGH 3
92+
9693

9794
/** End of package independent params */
9895

@@ -102,6 +99,12 @@
10299
/** XO adjustment value */
103100
#define QFN_XO_VAL 0x2A
104101

102+
/** Systematic error between set power and measured power in dBm */
103+
#define QFN_SYSTEM_OFFSET_LB 3
104+
#define QFN_SYSTEM_OFFSET_HB_CHAN_LOW 3
105+
#define QFN_SYSTEM_OFFSET_HB_CHAN_MID 3
106+
#define QFN_SYSTEM_OFFSET_HB_CHAN_HIGH 3
107+
105108
/** Max TX power allowed for DSSS and OFDM in 2.4GHz band */
106109
#define QFN_MAX_TX_PWR_DSSS 0x54
107110
#define QFN_MAX_TX_PWR_LB_MCS7 0x40
@@ -154,24 +157,29 @@
154157
/** XO adjustment value */
155158
#define CSP_XO_VAL 0x2A
156159

160+
/** Systematic error between set power and measured power in dBm */
161+
#define CSP_SYSTEM_OFFSET_LB 5
162+
#define CSP_SYSTEM_OFFSET_HB_CHAN_LOW 5
163+
#define CSP_SYSTEM_OFFSET_HB_CHAN_MID 5
164+
#define CSP_SYSTEM_OFFSET_HB_CHAN_HIGH 5
157165
/** Max TX power allowed for DSSS and OFDM in 2.4GHz band */
158-
#define CSP_MAX_TX_PWR_DSSS 0x48
159-
#define CSP_MAX_TX_PWR_LB_MCS7 0x44
160-
#define CSP_MAX_TX_PWR_LB_MCS0 0x44
166+
#define CSP_MAX_TX_PWR_DSSS 0x40
167+
#define CSP_MAX_TX_PWR_LB_MCS7 0x3C
168+
#define CSP_MAX_TX_PWR_LB_MCS0 0x3C
161169

162170
/** Max TX power allowed for MCS7 for channels in the range,
163171
* 36 to 64, 96 to 132 and 136 to 177
164172
*/
165-
#define CSP_MAX_TX_PWR_HB_LOW_CHAN_MCS7 0x3C
166-
#define CSP_MAX_TX_PWR_HB_MID_CHAN_MCS7 0x3C
167-
#define CSP_MAX_TX_PWR_HB_HIGH_CHAN_MCS7 0x3C
173+
#define CSP_MAX_TX_PWR_HB_LOW_CHAN_MCS7 0x34
174+
#define CSP_MAX_TX_PWR_HB_MID_CHAN_MCS7 0x34
175+
#define CSP_MAX_TX_PWR_HB_HIGH_CHAN_MCS7 0x34
168176

169177
/** Max TX power allowed for MCS0 for channels in the range,
170178
* 36 to 64, 96 to 132 and 136 to 177
171179
*/
172-
#define CSP_MAX_TX_PWR_HB_LOW_CHAN_MCS0 0x3C
173-
#define CSP_MAX_TX_PWR_HB_MID_CHAN_MCS0 0x3C
174-
#define CSP_MAX_TX_PWR_HB_HIGH_CHAN_MCS0 0x3C
180+
#define CSP_MAX_TX_PWR_HB_LOW_CHAN_MCS0 0x34
181+
#define CSP_MAX_TX_PWR_HB_MID_CHAN_MCS0 0x34
182+
#define CSP_MAX_TX_PWR_HB_HIGH_CHAN_MCS0 0x34
175183

176184
/** Max chip temperature at which the TX power backoff to be applied. */
177185
#define CSP_MAX_CHIP_TEMP 0x43

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