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[nrf fromtree] platform: nordic_nrf: Add mramc service for nrf7120
nrf7120 zephyr mramc driver needs to access some configuration registers in mramc which is secure only, nrf_mramc service is created to access MRAMC initialise and change write config of mramc. MRAMC service functions is added under iotcl service type. Change-Id: I93e411a0a51c8d96f1c5239efa006afab304c72e Signed-off-by: Travis Lam <travis.lam@nordicsemi.no> (cherry picked from commit 66503e7c7c9d644f39a9ca35550d6c5af4792cd5)
1 parent 320f052 commit 11b0aa5

5 files changed

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platform/ext/target/nordic_nrf/common/core/CMakeLists.txt

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@@ -165,6 +165,13 @@ if(TFM_SPM_LOG_RAW_ENABLED OR SECURE_UART1)
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)
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endif()
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if(TFM_NRF_MRAMC_SERVICE)
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target_compile_definitions(platform_s
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PUBLIC
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TFM_NRF_MRAMC_SERVICE
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)
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endif()
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target_compile_options(platform_s
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PUBLIC
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${COMPILER_CMSE_FLAG}

platform/ext/target/nordic_nrf/common/core/services/include/tfm_ioctl_core_api.h

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@@ -31,6 +31,8 @@ enum tfm_platform_ioctl_core_reqest_types_t {
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TFM_PLATFORM_IOCTL_READ_SERVICE,
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TFM_PLATFORM_IOCTL_WRITE32_SERVICE,
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TFM_PLATFORM_IOCTL_GPIO_SERVICE,
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TFM_PLATFORM_IOCTL_MRAMC_INIT_SERVICE,
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TFM_PLATFORM_IOCTL_MRAMC_SET_WEN_SERVICE,
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/* Last core service, start platform specific from this value. */
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TFM_PLATFORM_IOCTL_CORE_LAST
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};
@@ -89,6 +91,12 @@ struct tfm_gpio_service_out {
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uint32_t result;
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};
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#if defined(CONFIG_TFM_NRF_MRAMC_SERVICE)
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struct tfm_mramc_set_wen_service_args_t {
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uint32_t write_mode;
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};
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#endif
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/**
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* @brief Perform a read operation.
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*
@@ -151,6 +159,25 @@ enum tfm_write32_service_result {
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enum tfm_platform_err_t tfm_platform_gpio_pin_mcu_select(uint32_t pin_number, uint32_t mcu,
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uint32_t *result);
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#if defined(CONFIG_TFM_NRF_MRAMC_SERVICE)
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/**
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* @brief Initialise MRAMC peripheral.
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*
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* @return On success the processor will initialise MRAMC, in case of error it returns
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* values as specified by the \ref tfm_platform_err_t
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*/
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enum tfm_platform_err_t tfm_platform_mramc_init(void);
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/**
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* @brief Setting write permission for MRAMC peripheral.
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*
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* @param write_mode Write mode for MRAMC peripheral.
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*
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* @return On success the processor will set MRAMC config write mode, in case of error it returns
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* values as specified by the \ref tfm_platform_err_t
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*/
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enum tfm_platform_err_t tfm_platform_mramc_set_wen(uint32_t write_mode);
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#endif /* TFM_NRF_MRAMC_SERVICE */
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#ifdef __cplusplus
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}

platform/ext/target/nordic_nrf/common/core/services/include/tfm_platform_hal_ioctl.h

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@@ -31,6 +31,12 @@ enum tfm_platform_err_t
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tfm_platform_hal_write32_service(const psa_invec *in_vec,
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const psa_outvec *out_vec);
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enum tfm_platform_err_t
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tfm_platform_hal_mramc_init_service(void);
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enum tfm_platform_err_t
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tfm_platform_hal_mramc_set_wen_service(const psa_invec *in_vec);
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#ifdef __cplusplus
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}
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#endif

platform/ext/target/nordic_nrf/common/core/services/src/tfm_ioctl_core_ns_api.c

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@@ -94,3 +94,26 @@ enum tfm_platform_err_t tfm_platform_mem_write32(uint32_t addr, uint32_t value,
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return ret;
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}
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#if defined(CONFIG_TFM_NRF_MRAMC_SERVICE)
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enum tfm_platform_err_t tfm_platform_mramc_init(void)
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{
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return tfm_platform_ioctl(TFM_PLATFORM_IOCTL_MRAMC_INIT_SERVICE, NULL,
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NULL);
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}
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enum tfm_platform_err_t tfm_platform_mramc_set_wen(uint32_t write_mode)
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{
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psa_invec in_vec;
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struct tfm_mramc_set_wen_service_args_t args;
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args.write_mode = write_mode;
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in_vec.base = (const void *)&args;
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in_vec.len = sizeof(struct tfm_mramc_set_wen_service_args_t);
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return tfm_platform_ioctl(TFM_PLATFORM_IOCTL_MRAMC_SET_WEN_SERVICE, &in_vec,
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NULL);
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}
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#endif

platform/ext/target/nordic_nrf/common/core/services/src/tfm_platform_hal_ioctl.c

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@@ -22,6 +22,10 @@
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#include <nrfx_nvmc.h>
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#endif
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#if TFM_NRF_MRAMC_SERVICE
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#include <nrfx_mramc.h>
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#endif
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#include "handle_attr.h"
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enum tfm_platform_err_t
@@ -232,3 +236,39 @@ enum tfm_platform_err_t tfm_platform_hal_write32_service(const psa_invec *in_vec
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return err;
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}
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#if TFM_NRF_MRAMC_SERVICE
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enum tfm_platform_err_t tfm_platform_hal_mramc_init_service(void)
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{
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nrfx_mramc_config_t config = NRFX_MRAMC_DEFAULT_CONFIG();
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int ret = nrfx_mramc_init(&config, NULL);
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if (ret == -EALREADY) {
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/* Driver is initialise by ITS or PS at the ealier stage*/
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return TFM_PLATFORM_ERR_SUCCESS;
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} else if (ret != 0) {
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return TFM_PLATFORM_ERR_SYSTEM_ERROR;
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}
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return TFM_PLATFORM_ERR_SUCCESS;
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}
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enum tfm_platform_err_t tfm_platform_hal_mramc_set_wen_service(const psa_invec *in_vec)
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{
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struct tfm_mramc_set_wen_service_args_t *args;
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if (in_vec->len != sizeof(struct tfm_mramc_set_wen_service_args_t)) {
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return TFM_PLATFORM_ERR_INVALID_PARAM;
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}
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args = (struct tfm_mramc_set_wen_service_args_t *)in_vec->base;
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uint32_t write_mode = args->write_mode;
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while(!nrfx_mramc_ready_check()) {
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/* Wait until MRAMC is ready for the next operation */
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}
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nrfx_mramc_config_write_mode_set(write_mode);
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return TFM_PLATFORM_ERR_SUCCESS;
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}
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#endif /* TFM_NRF_MRAMC_SERVICE */

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