[nrf noup] Add missing CPPWR for ARM V8M

This is a workaround, TF-M v2.3 introduced a
patch file for the CMSIS where it includes
missing definitions for CPPWR.

I don't want want to fork CMSIS just for that,
or try to update CMSIS for the whole Zephyr with
this PR. So I patched the relevant code for the
cortex-m33 in TF-M in the file that uses it.

This is not ideal but also not a big issue
because the patch has been submitted and merged
in the upstream repo:

ARM-software/CMSIS_6#243

So this commit can be dropped when Zephyr updates
to a version that includes this change.

Signed-off-by: Georgios Vasilakis <georgios.vasilakis@nordicsemi.no>

Author: Vge0rge

secure_fw/spm/core/arch/tfm_arch_v8m_main.c

@@ -23,6 +23,21 @@
 
 #include "compiler_ext_defs.h" /* Keep last. */
 
+#if defined(__ARM_ARCH_8M_MAIN__)
+/** \brief SCnSCB Coprocessor Power Control Register Definitions */
+#define SCnSCB_CPPWR_SUS11_Pos             23U                                         /*!< CPPWR: SUS11 Position */
+#define SCnSCB_CPPWR_SUS11_Msk             (1UL << SCnSCB_CPPWR_SUS11_Pos)             /*!< CPPWR: SUS11 Mask */
+
+#define SCnSCB_CPPWR_SU11_Pos              22U                                         /*!< CPPWR: SU11 Position */
+#define SCnSCB_CPPWR_SU11_Msk              (1UL << SCnSCB_CPPWR_SU11_Pos)              /*!< CPPWR: SU11 Mask */
+
+#define SCnSCB_CPPWR_SUS10_Pos             21U                                         /*!< CPPWR: SUS10 Position */
+#define SCnSCB_CPPWR_SUS10_Msk             (1UL << SCnSCB_CPPWR_SUS10_Pos)             /*!< CPPWR: SUS10 Mask */
+
+#define SCnSCB_CPPWR_SU10_Pos              20U                                         /*!< CPPWR: SU10 Position */
+#define SCnSCB_CPPWR_SU10_Msk              (1UL << SCnSCB_CPPWR_SU10_Pos)              /*!< CPPWR: SU10 Mask */
+#endif
+
 #if !defined(__ARM_ARCH_8M_MAIN__) && !defined(__ARM_ARCH_8_1M_MAIN__)
 #error "Unsupported ARM Architecture."
 #endif