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Expand file tree Collapse file tree Original file line number Diff line number Diff line change 1+ /*
2+ * Copyright (c) 2021, Arm Limited. All rights reserved.
3+ *
4+ * SPDX-License-Identifier: BSD-3-Clause
5+ *
6+ */
7+
8+ #ifndef __CORE_EXT_H__
9+ #define __CORE_EXT_H__
10+
11+ /* Coprocessor Power Control Register Definitions */
12+ #define SCnSCB_CPPWR_SUS11_Pos 23U /*!< CPPWR: SUS11 Position */
13+ #define SCnSCB_CPPWR_SUS11_Msk (1UL << SCnSCB_CPPWR_SUS11_Pos) /*!< CPPWR: SUS11 Mask */
14+
15+ #define SCnSCB_CPPWR_SU11_Pos 22U /*!< CPPWR: SU11 Position */
16+ #define SCnSCB_CPPWR_SU11_Msk (1UL << SCnSCB_CPPWR_SU11_Pos) /*!< CPPWR: SU11 Mask */
17+
18+ #define SCnSCB_CPPWR_SUS10_Pos 21U /*!< CPPWR: SUS10 Position */
19+ #define SCnSCB_CPPWR_SUS10_Msk (1UL << SCnSCB_CPPWR_SUS10_Pos) /*!< CPPWR: SUS10 Mask */
20+
21+ #define SCnSCB_CPPWR_SU10_Pos 20U /*!< CPPWR: SU10 Position */
22+ #define SCnSCB_CPPWR_SU10_Msk (1UL << SCnSCB_CPPWR_SU10_Pos) /*!< CPPWR: SU10 Mask */
23+
24+ #endif /* __CORE_EXT_H__ */
Original file line number Diff line number Diff line change @@ -322,6 +322,7 @@ void tfm_arch_config_extensions(void)
322322#endif /* defined(CONFIG_TFM_ENABLE_CP10CP11) */
323323
324324#if (CONFIG_TFM_FLOAT_ABI >= 1 )
325+
325326#ifdef CONFIG_TFM_LAZY_STACKING
326327 /* Enable lazy stacking. */
327328 FPU -> FPCCR |= FPU_FPCCR_LSPEN_Msk ;
@@ -347,10 +348,12 @@ void tfm_arch_config_extensions(void)
347348
348349 /* Prevent non-secure from modifying FPU’s power setting. */
349350#if defined(__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1 )
350- ICB -> CPPWR |= ICB_CPPWR_SUS11_Msk | ICB_CPPWR_SUS10_Msk ;
351+ ICB -> CPPWR |=
351352#else
352- SCnSCB -> CPPWR |= SCnSCB_CPPWR_SUS11_Msk | SCnSCB_CPPWR_SUS10_Msk ;
353+ SCnSCB -> CPPWR |=
353354#endif
355+ ICB_CPPWR_SUS11_Msk | ICB_CPPWR_SUS10_Msk ;
356+
354357#endif /* CONFIG_TFM_FLOAT_ABI >= 1 */
355358
356359#if defined(__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1 ) && \
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