Kconfig

# ARM64 core configuration options

# Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
# SPDX-License-Identifier: Apache-2.0

config CPU_CORTEX_A
	bool
	select CPU_CORTEX
	select HAS_FLASH_LOAD_OFFSET
	select SCHED_IPI_SUPPORTED if SMP
	select CPU_HAS_FPU
	select ARCH_HAS_SINGLE_THREAD_SUPPORT if !SMP
	select CPU_HAS_DCACHE
	select CPU_HAS_ICACHE
	imply FPU
	imply FPU_SHARING
	help
	  This option signifies the use of a CPU of the Cortex-A family.

config CPU_AARCH64_CORTEX_R
	bool
	select CPU_CORTEX
	select HAS_FLASH_LOAD_OFFSET
	select CPU_HAS_DCACHE
	select CPU_HAS_ICACHE
	select ARCH_HAS_STACK_PROTECTION
	select CPU_HAS_FPU
	imply FPU
	imply FPU_SHARING
	help
	  This option signifies the use of a CPU of the Cortex-R 64-bit family.

config CPU_CORTEX_A53
	bool
	select CPU_CORTEX_A
	select ARMV8_A
	help
	  This option signifies the use of a Cortex-A53 CPU

config CPU_CORTEX_A55
	bool
	select CPU_CORTEX_A
	select ARMV8_A
	help
	  This option signifies the use of a Cortex-A55 CPU

config CPU_CORTEX_A57
	bool
	select CPU_CORTEX_A
	select ARMV8_A
	help
	  This option signifies the use of a Cortex-A57 CPU

config CPU_CORTEX_A72
	bool
	select CPU_CORTEX_A
	select ARMV8_A
	help
	  This option signifies the use of a Cortex-A72 CPU

config CPU_CORTEX_A76
	bool
	select CPU_CORTEX_A
	select ARMV8_A
	help
	  This option signifies the use of a Cortex-A76 CPU

config CPU_CORTEX_A76_A55
	bool
	select CPU_CORTEX_A
	select ARMV8_A
	help
	  This option signifies the use of a Cortex-A76 and A55 big little CPU cluster

config CPU_CORTEX_A78
	bool
	select CPU_CORTEX_A
	select ARMV8_A
	help
	  This option signifies the use of a Cortex-A78 CPU

config CPU_CORTEX_A510
	bool
	select CPU_CORTEX_A
	select ARMV9_A
	help
	  This option signifies the use of a Cortex-A510 CPU, which is Arm's
	  efficiency core implementing the ARMv9-A architecture. It provides
	  power-efficient processing optimized for embedded applications with
	  ARMv9-A features.

config CPU_CORTEX_A320
	bool
	select CPU_CORTEX_A
	select ARMV9_A
	help
	  This option signifies the use of a Cortex-A320 CPU, which implements
	  the ARMv9.2-A architecture. It provides advanced features including
	  enhanced SVE2, improved security extensions, and specialized performance
	  optimizations.

config CPU_CORTEX_R82
	bool
	select CPU_AARCH64_CORTEX_R
	select ARMV8_R
	help
	  This option signifies the use of a Cortex-R82 CPU

config HAS_ARM_SMCCC
	bool
	help
	  Include support for the Secure Monitor Call (SMC) and Hypervisor
	  Call (HVC) instructions on Armv7 and above architectures.

config NUM_IRQS
	int

config MAIN_STACK_SIZE
	default 4096

config IDLE_STACK_SIZE
	default 4096

config PRIVILEGED_STACK_SIZE
	default 4096 if FPU_SHARING
	default 2048

config ISR_STACK_SIZE
	default 4096

config TEST_EXTRA_STACK_SIZE
	default 4096 if FPU_SHARING
	default 2048

config SYSTEM_WORKQUEUE_STACK_SIZE
	default 4096

config CMSIS_THREAD_MAX_STACK_SIZE
	default 4096

config CMSIS_V2_THREAD_MAX_STACK_SIZE
	default 4096

config CMSIS_V2_THREAD_DYNAMIC_STACK_SIZE
	default 4096

config IPM_CONSOLE_STACK_SIZE
	default 2048

config AARCH64_IMAGE_HEADER
	bool "Add image header"
	default y if ARM_MMU || ARM_MPU
	help
	  This option enables standard ARM64 boot image header used by Linux
	  and understood by loaders such as u-boot on Xen xl tool.

config PRIVILEGED_STACK_SIZE
	default 4096

config KOBJECT_TEXT_AREA
	default 1024 if UBSAN
	default 512 if TEST

config WAIT_AT_RESET_VECTOR
	bool "Wait at reset vector"
	default n
	help
	  Spin at reset vector waiting for debugger to attach and resume
	  execution

config ARM64_SAFE_EXCEPTION_STACK
	bool "To enable the safe exception stack"
	help
	  The safe exception stack is used for checking whether the kernel stack
	  overflows during the exception happens from EL1. This stack is not
	  used for user stack overflow checking, because kernel stack support
	  the checking work.

config ARM64_SAFE_EXCEPTION_STACK_SIZE
	int "The stack size of the safe exception stack"
	default 4096
	depends on ARM64_SAFE_EXCEPTION_STACK
	help
	  The stack size of the safe exception stack. The safe exception stack
	  requires to be enough to do the stack overflow check.

config ARM64_FALLBACK_ON_RESERVED_CORES
	bool "To enable fallback on reserved cores"
	help
	  Give the ability to define more cores in the device tree than required
	  via CONFIG_MP_MAX_NUM_CPUS.  The extra cores in the device tree
	  become reserved.  If there is an issue powering on a core during boot
	  then that core will be skipped and the next core in the device tree
	  will be used.

config ARM64_STACK_PROTECTION
	bool
	default y if HW_STACK_PROTECTION
	depends on ARM_MPU
	select THREAD_STACK_INFO
	select ARM64_SAFE_EXCEPTION_STACK
	help
	  This option leverages the MMU or MPU to cause a system fatal error if
	  the bounds of the current process stack are overflowed. This is done
	  by preceding all stack areas with a fixed guard region.

if CPU_CORTEX_A

config ARCH_HAS_STACKWALK
	bool
	default y
	depends on FRAME_POINTER
	help
	  Internal config to indicate that the arch_stack_walk() API is implemented
	  and it can be enabled.

config ARMV8_A_NS
	bool "ARMv8-A Normal World (Non-Secure world of Trustzone)"
	help
	  This option signifies that Zephyr is entered in TrustZone
	  Non-Secure state

config ARMV8_A
	bool
	select ATOMIC_OPERATIONS_BUILTIN
	select CPU_HAS_MMU
	select ARCH_HAS_USERSPACE if ARM_MMU
	select ARCH_HAS_NOCACHE_MEMORY_SUPPORT if ARM_MMU
	help
	  This option signifies the use of an ARMv8-A processor
	  implementation.

	  From https://developer.arm.com/products/architecture/cpu-architecture/a-profile:
	  The Armv8-A architecture introduces the ability to use 64-bit and
	  32-bit Execution states, known as AArch64 and AArch32 respectively.
	  The AArch64 Execution state supports the A64 instruction set, holds
	  addresses in 64-bit registers and allows instructions in the base
	  instruction set to use 64-bit registers for their processing. The AArch32
	  Execution state is a 32-bit Execution state that preserves backwards
	  compatibility with the Armv7-A architecture and enhances that profile
	  so that it can support some features included in the AArch64 state.
	  It supports the T32 and A32 instruction sets.

config ARMV9_A
	bool
	select ATOMIC_OPERATIONS_BUILTIN
	select CPU_HAS_MMU
	select ARCH_HAS_USERSPACE if ARM_MMU
	select ARCH_HAS_NOCACHE_MEMORY_SUPPORT if ARM_MMU
	imply ARM64_SVE if FPU_SHARING
	help
	  This option signifies the use of an ARMv9-A processor
	  implementation.
	  ARMv9-A builds on ARMv8-A and introduces additional security,
	  performance, and machine learning capabilities while maintaining
	  backward compatibility with ARMv8-A software.

rsource "xen/Kconfig"

endif # CPU_CORTEX_A

if CPU_AARCH64_CORTEX_R

config ARMV8_R
	bool
	select ATOMIC_OPERATIONS_BUILTIN
	select SCHED_IPI_SUPPORTED if SMP
	select ARCH_HAS_USERSPACE if ARM_MPU
	help
	  This option signifies the use of an ARMv8-R processor
	  implementation.

	  From https://developer.arm.com/products/architecture/cpu-architecture/r-profile:
	  The Armv8-R architecture targets at the Real-time profile. It introduces
	  virtualization at the highest security level while retaining the
	  Protected Memory System Architecture (PMSA) based on a Memory Protection
	  Unit (MPU). It supports the A32 and T32 instruction sets.

rsource "cortex_r/Kconfig"

endif # CPU_AARCH64_CORTEX_R

if CPU_CORTEX_A || CPU_AARCH64_CORTEX_R

config GEN_ISR_TABLES
	default y

config GEN_IRQ_VECTOR_TABLE
	default n

config ARM_MMU
	bool "ARM MMU Support"
	default n if CPU_AARCH64_CORTEX_R
	default y
	select MMU
	select SRAM_REGION_PERMISSIONS
	select ARCH_MEM_DOMAIN_SYNCHRONOUS_API if USERSPACE
	select ARCH_MEM_DOMAIN_DATA if USERSPACE
	select ARCH_MEM_DOMAIN_SUPPORTS_DEINIT if USERSPACE
	help
	  Memory Management Unit support.

config XIP
	select AARCH64_IMAGE_HEADER

config ARM64_SET_VMPIDR_EL2
	bool "Set VMPIDR_EL2 at EL2 stage"
	help
	  VMPIDR_EL2 holds the value of the Virtualization Multiprocessor ID.
	  This is the value returned by EL1 reads of MPIDR_EL1.
	  This register may already be set by bootloader at the EL2 stage, if
	  not, Zephyr should set it.

if ARM_MMU

config MMU_PAGE_SIZE
	default 0x1000

choice ARM64_VA_BITS
	prompt "Virtual address space size"
	default ARM64_VA_BITS_32
	help
	  Allows choosing one of multiple possible virtual address
	  space sizes. The level of translation table is determined by
	  a combination of page size and virtual address space size.

config ARM64_VA_BITS_32
	bool "32-bit"

config ARM64_VA_BITS_36
	bool "36-bit"

config ARM64_VA_BITS_40
	bool "40-bit"

config ARM64_VA_BITS_42
	bool "42-bit"

config ARM64_VA_BITS_48
	bool "48-bit"
endchoice

config ARM64_VA_BITS
	int
	default 32 if ARM64_VA_BITS_32
	default 36 if ARM64_VA_BITS_36
	default 40 if ARM64_VA_BITS_40
	default 42 if ARM64_VA_BITS_42
	default 48 if ARM64_VA_BITS_48

choice ARM64_PA_BITS
	prompt "Physical address space size"
	default ARM64_PA_BITS_32
	help
	  Choose the maximum physical address range that the kernel will
	  support.

config ARM64_PA_BITS_32
	bool "32-bit"

config ARM64_PA_BITS_36
	bool "36-bit"

config ARM64_PA_BITS_40
	bool "40-bit"

config ARM64_PA_BITS_42
	bool "42-bit"

config ARM64_PA_BITS_48
	bool "48-bit"
endchoice

config ARM64_PA_BITS
	int
	default 32 if ARM64_PA_BITS_32
	default 36 if ARM64_PA_BITS_36
	default 40 if ARM64_PA_BITS_40
	default 42 if ARM64_PA_BITS_42
	default 48 if ARM64_PA_BITS_48

config MAX_XLAT_TABLES
	int "Maximum numbers of translation tables"
	default 32 if USERSPACE && TEST && SMP
	default 28 if USERSPACE && TEST
	default 20 if USERSPACE && (ARM64_VA_BITS >= 40)
	default 16 if USERSPACE
	default 12 if (ARM64_VA_BITS >= 40)
	default 8
	help
	  This option specifies the maximum numbers of translation tables.
	  Based on this, translation tables are allocated at compile time and
	  used at runtime as needed.  If the runtime need exceeds preallocated
	  numbers of translation tables, it will result in assert. Number of
	  translation tables required is decided based on how many discrete
	  memory regions (both normal and device memory) are present on given
	  platform and how much granularity is required while assigning
	  attributes to these memory regions.

endif # ARM_MMU

config ARM64_DCACHE_ALL_OPS
	bool "Provide data cache APIs to operate all data caches"
	depends on CACHE_MANAGEMENT && DCACHE
	help
	  Enable this option to provide the data cache APIs to flush or
	  invalidate all data caches.

config ARM64_BOOT_DISABLE_DCACHE
	bool "Disable data cache before enable MMU when booting from EL2"
	depends on ARM64_DCACHE_ALL_OPS
	help
	  To make it safe, if data cache is enabled in case of Zephyr is booting
	  from EL2, enable this option, it will clean and invalidate all data
	  cache and then disable data cache, it will will be re-enabled after
	  MMU is configured and enabled.

config ARM64_SVE
	bool "Scalable Vector Extension (SVE) support"
	depends on ARMV9_A
	help
	  Enable support for ARM64 Scalable Vector Extension (SVE).
	  This allows threads to use SVE/SVE2 instructions and automatically
	  handles context switching of SVE registers (Z0-Z31, P0-P15, FFR)
	  if CONFIG_FPU_SHARING is also set. Requires ARMv9-A architecture.

config ARM64_SVE_VL_MAX
	int "Maximum SVE vector length in bytes"
	depends on ARM64_SVE
	default 16
	range 16 256
	help
	  Maximum supported SVE vector length in bytes. This determines
	  the SVE context size within each thread structure. Valid values
	  are any power of two from 16 to 256 inclusive (128 to 2048 bits).
	  This can be smaller than the hardware supported vector length to
	  save some per-thread memory in which case the hardware will be
	  limited to the specified length. Having a larger value than what
	  the hardware supports will only waste memory.

endif # CPU_CORTEX_A || CPU_AARCH64_CORTEX_R