55 */
66#include "nrfx_gppi_sd2ppi_global.h"
77#include <ironside/se/api.h>
8+ #include <zephyr/sys/printk.h>
89
910static nrfx_atomic_t channels [NRFX_GPPI_NODE_COUNT ];
1011static nrfx_atomic_t group_channels [NRFX_GPPI_NODE_DPPI_COUNT ];
@@ -420,8 +421,8 @@ static int actual_channel_mask(nrfx_gppi_node_id_t node_id, uint32_t *ch_mask, b
420421 NRF_SPU133 ,
421422 NRF_SPU134 ,
422423 NRF_SPU135 ,
423- IF_ENABLED (NRFX_INSTANCE_PRESENT ( SPU136 ), (NRF_SPU136 ,))
424- IF_ENABLED (NRFX_INSTANCE_PRESENT ( SPU137 ), (NRF_SPU137 ,))
424+ IF_ENABLED (DT_NODE_EXISTS ( DT_NODELABEL ( dppic135 ) ), (NRF_SPU136 ,))
425+ IF_ENABLED (DT_NODE_EXISTS ( DT_NODELABEL ( dppic136 ) ), (NRF_SPU137 ,))
425426 NRF_SPU122 ,
426427 };
427428 uint32_t out_mask = 0 ;
@@ -443,7 +444,13 @@ static int actual_channel_mask(nrfx_gppi_node_id_t node_id, uint32_t *ch_mask, b
443444 entries_count ++ ;
444445 if ((entries_count == ARRAY_SIZE (entries )) || (in_mask == 0 )) {
445446 /* Read batch of registers. */
447+ printk ("Periphconf read: " );
448+ for (int i = 0 ; i < entries_count ; i ++ ) {
449+ printk ("reg: %08x, " , entries [i ].regptr );
450+ }
451+ printk ("\n" );
446452 status = ironside_se_periphconf_read (entries , entries_count );
453+ printk ("Periphconf read result: %d\n" , status .status );
447454 if (status .status == 0 ) {
448455 for (uint32_t i = 0 ; i < entries_count ; i ++ ) {
449456 /* If SPU register has default value assume that channel
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