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tmp: Add logs to gppi init
1 parent e88cd52 commit 7c0ebf7

2 files changed

Lines changed: 12 additions & 4 deletions

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soc/nordic/common/gppi_init.c

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -144,10 +144,11 @@ static int gppi_init(void)
144144
#if defined(CONFIG_NRFX_GPPI) && !defined(CONFIG_NRFX_GPPI_V1)
145145

146146
/* For nrf54h20 GPPI requires that ironside communication is up so delay the initialization. */
147-
#define GPPI_INIT_STATE COND_CODE_1(IS_ENABLED(CONFIG_SOC_NRF54H20_CPUAPP), (POST_KERNEL), (EARLY))
147+
#define GPPI_INIT_STATE \
148+
COND_CODE_1(IS_ENABLED(CONFIG_NRFX_GPPI_SD2PPI_GLOBAL), (POST_KERNEL), (EARLY))
148149

149150
#define GPPI_INIT_PRIO \
150-
COND_CODE_1(IS_ENABLED(CONFIG_SOC_NRF54H20_CPUAPP), \
151+
COND_CODE_1(IS_ENABLED(CONFIG_NRFX_GPPI_SD2PPI_GLOBAL), \
151152
(UTIL_INC(CONFIG_IRONSIDE_SE_CALL_INIT_PRIORITY)), (0))
152153

153154
SYS_INIT(gppi_init, GPPI_INIT_STATE, GPPI_INIT_PRIO);

soc/nordic/common/nrfx_gppi_sd2ppi_global.c

Lines changed: 9 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,7 @@
55
*/
66
#include "nrfx_gppi_sd2ppi_global.h"
77
#include <ironside/se/api.h>
8+
#include <zephyr/sys/printk.h>
89

910
static nrfx_atomic_t channels[NRFX_GPPI_NODE_COUNT];
1011
static nrfx_atomic_t group_channels[NRFX_GPPI_NODE_DPPI_COUNT];
@@ -420,8 +421,8 @@ static int actual_channel_mask(nrfx_gppi_node_id_t node_id, uint32_t *ch_mask, b
420421
NRF_SPU133,
421422
NRF_SPU134,
422423
NRF_SPU135,
423-
IF_ENABLED(NRFX_INSTANCE_PRESENT(SPU136), (NRF_SPU136,))
424-
IF_ENABLED(NRFX_INSTANCE_PRESENT(SPU137), (NRF_SPU137,))
424+
IF_ENABLED(DT_NODE_EXISTS(DT_NODELABEL(dppic135)), (NRF_SPU136,))
425+
IF_ENABLED(DT_NODE_EXISTS(DT_NODELABEL(dppic136)), (NRF_SPU137,))
425426
NRF_SPU122,
426427
};
427428
uint32_t out_mask = 0;
@@ -443,7 +444,13 @@ static int actual_channel_mask(nrfx_gppi_node_id_t node_id, uint32_t *ch_mask, b
443444
entries_count++;
444445
if ((entries_count == ARRAY_SIZE(entries)) || (in_mask == 0)) {
445446
/* Read batch of registers. */
447+
printk("Periphconf read: ");
448+
for (int i = 0; i < entries_count; i++) {
449+
printk("reg: %08x, ", entries[i].regptr);
450+
}
451+
printk("\n");
446452
status = ironside_se_periphconf_read(entries, entries_count);
453+
printk("Periphconf read result: %d\n", status.status);
447454
if (status.status == 0) {
448455
for (uint32_t i = 0; i < entries_count; i++) {
449456
/* If SPU register has default value assume that channel

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