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tmp: Add logs to gppi init
1 parent e88cd52 commit f8ad3a5

3 files changed

Lines changed: 18 additions & 4 deletions

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modules/hal_nordic/nrfx/nrfx_kconfig.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -438,6 +438,10 @@
438438
#define NRFX_WDT_CONFIG_LOG_ENABLED 1
439439
#endif
440440

441+
#ifdef CONFIG_NRFX_GPPI_SD2PPI_GLOBAL
442+
#define NRFX_GPPI_CONFIG_DPPI_PPIB_EXT_FUNC 1
443+
#endif
444+
441445
#ifdef CONFIG_NRF52_ANOMALY_109_WORKAROUND
442446
#define NRF52_ERRATA_109_ENABLE_WORKAROUND 1
443447
#define NRFX_PWM_NRF52_ANOMALY_109_EGU_INSTANCE \

soc/nordic/common/gppi_init.c

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -144,10 +144,11 @@ static int gppi_init(void)
144144
#if defined(CONFIG_NRFX_GPPI) && !defined(CONFIG_NRFX_GPPI_V1)
145145

146146
/* For nrf54h20 GPPI requires that ironside communication is up so delay the initialization. */
147-
#define GPPI_INIT_STATE COND_CODE_1(IS_ENABLED(CONFIG_SOC_NRF54H20_CPUAPP), (POST_KERNEL), (EARLY))
147+
#define GPPI_INIT_STATE \
148+
COND_CODE_1(IS_ENABLED(CONFIG_NRFX_GPPI_SD2PPI_GLOBAL), (POST_KERNEL), (EARLY))
148149

149150
#define GPPI_INIT_PRIO \
150-
COND_CODE_1(IS_ENABLED(CONFIG_SOC_NRF54H20_CPUAPP), \
151+
COND_CODE_1(IS_ENABLED(CONFIG_NRFX_GPPI_SD2PPI_GLOBAL), \
151152
(UTIL_INC(CONFIG_IRONSIDE_SE_CALL_INIT_PRIORITY)), (0))
152153

153154
SYS_INIT(gppi_init, GPPI_INIT_STATE, GPPI_INIT_PRIO);

soc/nordic/common/nrfx_gppi_sd2ppi_global.c

Lines changed: 11 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,7 @@
55
*/
66
#include "nrfx_gppi_sd2ppi_global.h"
77
#include <ironside/se/api.h>
8+
#include <stdio.h>
89

910
static nrfx_atomic_t channels[NRFX_GPPI_NODE_COUNT];
1011
static nrfx_atomic_t group_channels[NRFX_GPPI_NODE_DPPI_COUNT];
@@ -420,8 +421,8 @@ static int actual_channel_mask(nrfx_gppi_node_id_t node_id, uint32_t *ch_mask, b
420421
NRF_SPU133,
421422
NRF_SPU134,
422423
NRF_SPU135,
423-
IF_ENABLED(NRFX_INSTANCE_PRESENT(SPU136), (NRF_SPU136,))
424-
IF_ENABLED(NRFX_INSTANCE_PRESENT(SPU137), (NRF_SPU137,))
424+
IF_ENABLED(DT_NODE_EXISTS(DT_NODELABEL(dppic135)), (NRF_SPU136,))
425+
IF_ENABLED(DT_NODE_EXISTS(DT_NODELABEL(dppic136)), (NRF_SPU137,))
425426
NRF_SPU122,
426427
};
427428
uint32_t out_mask = 0;
@@ -513,6 +514,14 @@ int nrfx_gppi_ext_ppib_write(volatile uint32_t *p_addr, uint32_t value)
513514
}
514515

515516
status = ironside_se_periphconf_write(write_entries, write_entries_count);
517+
if (status.status < 0) {
518+
printf("write failed: %d\n", status.status);
519+
for (int i = 0; i < write_entries_count; i++) {
520+
printf("%d entry reg:%08x, val:%08x\n", (uint32_t)write_entries[i].regptr,
521+
write_entries[i].value);
522+
}
523+
}
524+
516525
write_entries_count = 0;
517526

518527
return (status.status < 0) ? -EIO : 0;

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