gul_host_if.h

/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
 * Copyright 2019-2024 NXP
 *
 */
#ifndef __GUL_HOST_IF_H__
#define __GUL_HOST_IF_H__
#include "rf_hif.h"
#include "hawk_hif.h"

#ifdef MODEM
#pragma pack(push, 1)
#endif

/*Common Addresses and offsets*/
#define GUL_PCI1_ADDR_BASE	(0x00000000U)
#define GUL_PCI1_ADDR_SIZE	(2U * 1024 * 1024 * 1024) /*2 GB*/
#define GUL_PCI2_ADDR_BASE	(0x80000000)
#define GUL_PCI2_ADDR_SIZE	(1 * 1024 * 1024 * 1024) /*1 GB*/
#define SPLIT_VA32_H(A) ((uint32_t)((uint64_t)(A)>>32))
#define SPLIT_VA32_L(A) ((uint32_t)((uint64_t)(A)))

/* Set GUL_QDMA_FOR_BOOT_ENABLE to 1 to enable bootrom to use QDMA for copying images to gul side */
#define GUL_QDMA_FOR_BOOT_ENABLE		0

/* Host Physical addresses exposed to Modem. Addresses defined below are view
 * of host physical addresses in Modem address space (PCIe). Following are
 * the exposed Physical addresses:
 * 1. MSI - MSI addresses of host.
 * 2. SCRATCH buf - used for L1Trace, Modem logging.
 * 3. Huge Page  - User space Huge page for IPC.
 **/

/*
 * Assignment of Modem PCIe address space for Host, Memories
 */
#define GUL_EP_TO_HOST_MSI_SIZE		(64 * 1024) /*64 KB*/

/** map for 2GB PCIe address space
 * ++++++++++++++++++++++++++++++++++++++
 * + Huge page /IPC (remaining)         +
 * ++++++++++++++++++++++++++++++++++++++
 * + Scratch buffer (user configurable) +
 * ++++++++++++++++++++++++++++++++++++++
 * + MSI Buffer (64KB)		+
 * ++++++++++++++++++++++++++++++++++++++
 */

/*User space Huge page*/
#define GUL_USER_HUGE_PAGE_OFFSET	(0)

#define GUL_USER_HUGE_PAGE_ADDR	(GUL_PCI1_ADDR_BASE + GUL_USER_HUGE_PAGE_OFFSET)

#define GUL_EP_TOHOST_MSI_OFFSET	   (GUL_PCI1_ADDR_SIZE - \
					GUL_EP_TO_HOST_MSI_SIZE)

#define GUL_EP_TOHOST_MSI_PHY_ADDR	(GUL_PCI1_ADDR_BASE +\
					GUL_EP_TOHOST_MSI_OFFSET)

/* SCRATCH Buffer */
#define GUL_SCRATCH_DMA_BUF_END_ADDR	(GUL_EP_TOHOST_MSI_OFFSET)
#define GUL_EP_BOOT_HDR_OFFSET	(0x00000000)
#define GUL_MSI_MAX_CNT		8
#define GUL_QDMA_CHANNELS	14
#define GUL_VSPA_CORE_MAX	8
#define MIN_THRESHOLD_COUNT	1
#define MAX_THRESHOLD_COUNT	2

#define GEUL_SVR_UNKNOWN_VAL	0x0
#define GEUL_SVR_REVA_VAL	(0x81520000)
#define GEUL_SVR_REVB_VAL	(0x81530000)
#define GEUL_SVR_REV_MASK	(0xffff0000)

#define GEUL_SVR_HSDCS_NO	(0x400)
#define GEUL_SVR_HSDCS_RXONLY	(0x200)
#define GEUL_SVR_HSDCS_FULL	(0x000)
#define GEUL_SVR_HSDCS_MASK	(0x600)

#define GEUL_E200_CORE_REVA_NUM   4
#define GEUL_E200_CORE_REVB_NUM   6

#define gul_ep_get_soc_rev()	(ioread32be(&hif->soc_rev) & GEUL_SVR_REV_MASK)
#define gul_ep_get_hsdcs_type()	(ioread32be(&hif->soc_rev) & GEUL_SVR_HSDCS_MASK)
#define gul_ep_get_svr()	(ioread32be(&hif->soc_rev))
#define gul_ep_get_numcores()	(ioread32be(&hif->soc_numcores))

#define GEUL_HOST_UNKNOWN_VAL	0x0
#define GEUL_HOST_REVA_VAL	0x1
#define GEUL_HOST_REVB_VAL	0x2
#define GEUL_HOST_REVC_VAL	0x3

/* this API is only implemented for LA1224, will return GEUL_HOST_UNKNOWN_VAL for other platforms */
#define get_host_board_rev()		(in_le32(&pHif->host_board_rev))

#define MPIC_BASE_ADDRESS	0x2040000
#define MPIC_REG_MSIIR		0x01740
#define MPIC_REG_MSIIRB		0x01940
#define MPIC_REG_MSIIRC		0x01B40
#define MPIC_MSIIR_SRS_BIT	29
#define MPIC_MSIIR_IBS_BIT	24

/* Stats Control */
#define GUL_AVI_STATS_ENABLE	0

enum gul_msi_id {
	MSI_IRQ_MUX = 0,
	MSI_IRQ_UNUSED_1,
	MSI_IRQ_UNUSED_2,
	MSI_IRQ_UNUSED_3,
	MSI_IRQ_UNUSED_4,
	MSI_IRQ_UNUSED_5,
	MSI_IRQ_UNUSED_6,
	MSI_IRQ_UNUSED_7,
	MSI_IRQ_COUNT,
};

enum scratch_buf_request_id {
	GUL_SCRATCH_MODEM_SHARE = 0,
	GUL_HOST_DATA,
	GUL_RF_DATA,
	GUL_FIRMWARE,
	GUL_SCRATCH_DBG_LOGGER,
	GUL_VSPA_FW,
	GUL_VSPA_OVERLAY,
	GUL_SCRATCH_END,
};

enum gul_msg_unit_id {
	GUL_MSG_UNIT_1 = 0,
	GUL_MSG_UNIT_2,
	GUL_MSG_UNIT3,
	GUL_MSG_UNIT_CNT,
};

#define GUL_DMA_OUTBOUND_WIN	OUTBOUND_0
#define GUL_MSI_OUTBOUND_WIN	OUTBOUND_1
#define GUL_V2H_OUTBOUND_WIN	OUTBOUND_2


#define GUL_IRQ_MUX_MSG_UNIT		GUL_MSG_UNIT_1
#define GUL_RFIC_SWCMD_MSG_UNIT		GUL_MSG_UNIT_1
#define BITMASK(n)			(1 << n)
#define GUL_IRQ_MUX_MSG_UNIT_BIT	(0)
#define GUL_RFIC_SWCMD_MSG_UNIT_BIT	(1)

#define GUL_IPC_MSG_UNIT		GUL_MSG_UNIT_2
#define GUL_IPC_CH_MSG_UNIT_BIT(n)	(1 << n)
#define GUL_IPC_CH0_MSG_UNIT_BIT	(0)
#define GUL_IPC_CH1_MSG_UNIT_BIT	(1)
#define GUL_IPC_CH2_MSG_UNIT_BIT	(2)
#define GUL_IPC_CH3_MSG_UNIT_BIT	(3)

#define GUL_WDOG_WARMUP_MODEM_RESET	1<<31

/* Number of IPC channels to create at run time */
//CPE #define IPC_MAX_CHANNEL_COUNT	(16)
/* Maximum size of data transfer supported in IPC CP */
/* Should be multiple of 4 */
#define IPC_MSG_SIZE		(0x100)		/* 256B */

/** No. of max channel per instance
  * 8 SE, 8 SD, 4 CE, 4 CD, 8 RAW */
#define IPC_MAX_CHANNEL_COUNT	(32)

/*TBD: This structure needs to be changed for MPIC message registers*/
struct gul_msg_unit {
	uint32_t msiir;
	uint32_t msir;
} __attribute__ ((packed));

/*Scratch register for Host <> GUL Boot hand shake*/
#define GUL_BOOT_HSHAKE_HIF_REG		9
#define GUL_BOOT_HSHAKE_HIF_SIZ_REG	10

enum gul_boot_fsm {
	NONE = 0,
	GUL_HOST_START_CLOCK_CONFIG,
	GUL_HOST_COMPLETE_CLOCK_CONFIG,
	GUL_HOST_START_DRIVER_INIT,
};

#define		PCIE_QDMA_DIS_MASK	0x00000001

struct sgtable {
	uint32_t len;
	uint32_t resv;
	uint32_t src;
	uint32_t dest;
};

struct cfword {
	uint32_t addr;
	uint32_t data;
};

struct gul_boot_header {
	uint32_t			preamble;
	uint32_t			sgentries;
	struct sgtable			sgtbl[8];
	uint32_t			bl_entry;
	uint32_t			flags;
	uint32_t			cfword_count;
	struct  cfword			cfwrd[128];
	uint32_t			target_boot_done;	   // for testing
} __attribute__ ((packed));
/*
struct gul_boot_header {
	uint32_t preamble;
	uint32_t plugin_size;
	uint32_t plugin_offset;
	uint32_t bl_size;
	uint32_t bl_src_offset;
	uint32_t bl_dest;
	uint32_t bl_entry;
	uint32_t reserved;
} __attribute__ ((packed));
*/
#define GUL_BOOT_HDR_BYPASS_BOOT_PLUGIN	(1 << 16)
#define GUL_BOOT_HDR_BYPASS_BOOT_EDMA	(1 << 0)

struct irq_evt_regs {
	uint32_t irq_evt_cfg;
	uint32_t irq_evt_en;
	uint32_t irq_evt_status;
	uint32_t irq_evt_clr;
	uint32_t vspa_evt_mask;
	uint32_t ipc_evt_mask;
	uint32_t test_evt_mask;
} __attribute__ ((packed));

#define GUL_EVT_UPDATE_EVT_CFG(pIrqEvtRegs, nIrqEvts) do {	\
	pIrqEvtRegs->irq_evt_cfg &= ~(0xff00);			\
	pIrqEvtRegs->irq_evt_cfg |= (nIrqEvts << 8);		\
} while (0)

#define GUL_EVT_SET_EVT_CFG(pIrqEvtRegs, nIrqWrds, nIrqEvts) do {	\
	pIrqEvtRegs->irq_evt_cfg = ((nIrqEvts << 8) | nIrqWrds);	\
} while (0)

#define GUL_DBG_LOG_MAX_STRLEN	(100)

struct debug_log_regs {
	uint64_t buf;
	uint64_t len;
	uint32_t log_level;
} __attribute__ ((packed));

#define GUL_LOG_LEVEL_ERR	1
#define GUL_LOG_LEVEL_INFO	2
#define GUL_LOG_LEVEL_DBG	3
#define GUL_LOG_LEVEL_ISR	4
#define GUL_LOG_LEVEL_ALL	5

struct gul_QDMA {
	uint32_t  status;
	uint32_t xfer_req;
	uint32_t success_interrupt;
	uint32_t error_interrupt;
	uint32_t no_callback_reg;
} __attribute__((packed));

struct gul_avi_stats {
	uint32_t irq_raise_count;
	uint32_t irq_clear_count;
	uint32_t irq_evt_cleared;
	uint32_t avi_E200_mbox0_tx_cnt;
	uint32_t avi_E200_mbox1_tx_cnt;
	uint32_t avi_E200_mbox0_rx_cnt;
	uint32_t avi_E200_mbox1_rx_cnt;
} __attribute__((packed));

struct gul_cpuidle_stats {
	volatile uint32_t strt1_l;
	volatile uint32_t strt1_h;
	volatile uint32_t strt2_l;
	volatile uint32_t strt2_h;
	volatile uint32_t s_cnt_l;
	volatile uint32_t s_cnt_h;
	volatile uint32_t status;
} __attribute__((packed));

struct gul_ipc_ch_stats {
	uint32_t err_not_implemented;/**< Not implemented functionality count */
	uint32_t num_of_msg_recved;  /**< Total number of messages received */
	uint32_t num_of_msg_sent;	/**< Total number of messages/ptr sent */
	uint32_t total_msg_length;   /**< Total message length */
	uint32_t err_input_invalid;
	uint32_t err_channel_invalid;
	uint32_t err_mem_invalid;
	uint32_t err_channel_full;
	uint32_t err_channel_empty;
	uint32_t err_buf_list_empty;
	uint32_t err_buf_list_full;
	uint32_t err_host_buf_alloc_fail;
	uint32_t err_ioctl_fail;
	uint32_t err_efd_reg_fail;
} __attribute__((packed));

struct gul_ipc_stats {
	uint32_t err_instance_invalid;
	uint32_t err_md_sz_mismatch;
	uint32_t err_mem_invalid;
	uint32_t err_input_invalid;
	struct gul_ipc_ch_stats ipc_ch_stats[IPC_MAX_CHANNEL_COUNT];
} __attribute__((packed));

struct gul_mpic_stats {
	uint32_t timer_irq_cnt;
	uint32_t msi_irq_cnt;
} __attribute__((packed));

struct gul_spinlock_stats {
	uint32_t spinlock_count;
} __attribute__((packed));

struct gul_stats {
	uint32_t disabled_evt_try_cnt;
	uint32_t eDMA_ch_allocated;
	struct gul_QDMA gul_QDMA_ch[GUL_QDMA_CHANNELS];
	uint32_t WDOG_interrupt;
	struct gul_ipc_stats m_ipc_stats;
	struct gul_ipc_stats h_ipc_stats;
	struct gul_mpic_stats mpic_stats;
	struct gul_spinlock_stats spinlock_stats;
	struct gul_cpuidle_stats cpuidle_stats[GUL_EP_CORE_MAX];
#if GUL_AVI_STATS_ENABLE
	struct gul_avi_stats vspa_avi_stats[GUL_VSPA_CORE_MAX];
#endif
} __attribute__((packed));

struct hif_ipc_regs {
	uint32_t ipc_mdata_offset;
	uint32_t ipc_mdata_size;
} __attribute__((packed));

struct hif_rfic_regs {
	uint32_t mdata_offset_reg;
	uint32_t mdata_size;
	uint32_t spi_access_disabled;
} __attribute__((packed));

enum host_mem_region_id {
	HOST_MEM_HUGE_PAGE_BUF = 0,
	HOST_MEM_SCRATCH_BUF,
	HOST_MEM_FECA_AXI_SLAVE,
	HOST_MEM_FECA_APB_SLAVE,
	HOST_MEM_END
};

struct host_mem_region {
	uint32_t mod_phys_l;
	uint32_t mod_phys_h;
	uint32_t size_l;
	uint32_t size_h;
} __attribute__((packed));

/* This enum will specify the dedicated MSI lines shared between
 * the host and EP (**MSI_IRQ_MAX_CNT cant be used as a MSI line)
 */
enum host_msi_id {
	HOST_MSI_TMU = 0,
	IPC_CHANNEL_IRQ1,
	IPC_CHANNEL_IRQ2,
	IPC_CHANNEL_IRQ3,
	HOST_CLI_IRQ,
	HOST_MSI_RTD,
	HOST_MSI_MTD_POWER,
	HOST_DCS_TMON_MSIA_7,
	HOST_MSI_MAX_IRQ_COUNT,
};

enum host_msib_id {
	MSI_RF_1 = 0,
	MSI_RF_2,
	MSI_RF_3,
	MSI_RF_4,
	MSI_RF_5,
	HOST_MSI_RF,
	HOST_UNUSED_MSIB_6,
	HOST_UNUSED_MSIB_7,
	HOST_MSIB_MAX_IRQ_COUNT,
};

enum msic_id {
	MSI_IG_1 = 0,
	MSI_IG_2,
	MSI_IG_3,
	MSI_IG_4,
	MSI_IG_5,
	MSI_IG_6,
	MSI_IG_7,
	MSI_IG_MAX_IRQ_COUNT,
};

#define HOST_MSI_HAWK	(IPC_CHANNEL_IRQ1)
/* Using IPC_CHANNEL_IRQ1.
 * It will be updated based on the availability of MSIs
 */
#define HOST_MSI_REFAPP (HOST_CLI_IRQ)

struct host_msi_unit {
	uint32_t msiir;
} __attribute__ ((packed));

enum mtd_eventID {
	TMU_HIGH_CRITICAL_TEMP_EVENT = 1,
	TMU_HIGH_TEMP_EVENT,
	TMU_LOW_TEMP_EVENT,
	TMU_LOW_CRIICAL_TEMP_EVENT,
	TMU_MAX_EVENT,
};

#define RTD_TEMP_INVALID	(0xffff)

enum rtd_eventID {
	TMU_RTD_HIGH_CRITICAL_TEMP_EVENT = 1,
	TMU_RTD_HIGH_TEMP_EVENT,
	TMU_RTD_LOW_TEMP_EVENT,
	TMU_RTD_LOW_CRIICAL_TEMP_EVENT,
	TMU_RTD_MAX_EVENT,
};

#define MTD_TEMP_INVALID	   (-70)

enum tvd_mtdEventId {
	TVD_MTD_CURENT_TEMP_REQUESTED = 1,
	TVD_MTD_CURENT_TEMP_REQUEST_ACKNOWLEDGED,
	TVD_MTD_HYSTERESIS_UPDATE_REQUESTED,
	TVD_MTD_HYSTERESIS_UPDATE_ACKNOWLEDGED,
	TVD_MTD_EVENT_MAX,
};

enum tvd_rtdEventId {
	TVD_RTD_CURENT_TEMP_REQUESTED = TVD_MTD_EVENT_MAX,
	TVD_RTD_CURENT_TEMP_REQUEST_ACKNOWLEDGED,
	TVD_RTD_HYSTERESIS_UPDATE_REQUESTED,
	TVD_RTD_HYSTERESIS_UPDATE_ACKNOWLEDGED,
	TVD_RTD_EVENT_MAX,
};

enum tvd_mtdPowerEventId {
	TVD_MTD_POWER_INFO_REQUESTED = TVD_RTD_EVENT_MAX,
	TVD_MTD_POWER_INFO_REQUEST_ACKNOWLEDGED,
	TVD_MTD_POWER_INFO_EVENT_MAX,
};

union mtdpowerInfo {
	struct {
		int16_t current_val;	/*<Current value from I2C sensor in mA.>*/
		int16_t shunt_volt;		/*<Shunt voltage value from I2C sensor in mV.>*/
		int16_t bus_volt;		/*<Bus voltage value from I2C sensor in mV.>*/
		int16_t power_val;		/*<Power value from I2C sensor in mW.>*/
	};
	struct {
		int32_t power_info_fh;	/*<Concatenated Value of current_val & shunt_volt. >*/
		int32_t power_info_sh;	/*<Concatenated Value of bus_volt & power_val. >*/
	};
	int64_t power_info;			/*<Concatenated Value of current_val, shunt_val, bus_volt & power_val>*/
} __attribute__((packed));

/* 
 *TEMP_ADJUST: temperature adjustment value. 
 *As the range of tmu is -40 to 160 and int8_t range is -128 to 127 so to
 *keep the temp within the int8_t range TEMP_ADJUST is being used.
 **/

#define TEMP_ADJUST 50

union mtdcurentTemp{
	struct {
		int8_t vspa_temp;
		int8_t feca_temp;
		int8_t pci_temp;
		int8_t diode_temp;
	};
	int32_t temp;
} __attribute__((packed));

struct mtd_thermalEvent {
	enum mtd_eventID tmuEvent;
	union  mtdcurentTemp curTemp;
} __attribute__ ((packed));

struct rtd_thermalEvent {
	enum rtd_eventID tmuEvent;
	uint32_t		 curTemp;
} __attribute__ ((packed));

struct tvd_mtd_threshold {
	uint32_t threshold_count;
	uint32_t threshold[MAX_THRESHOLD_COUNT];
} __attribute__ ((packed));

struct tvd_rtd_threshold {
	uint32_t threshold_count;
	uint32_t threshold[MAX_THRESHOLD_COUNT];
} __attribute__ ((packed));

enum dcs_eventID {
	HSADC_EVENT_RECAL_REQUESTED_ANT0 = 1,
	HSADC_EVENT_RECAL_REQ_ACK_ANT0,
	HSADC_EVENT_RECAL_REQUESTED_ANT1,
	HSADC_EVENT_RECAL_REQ_ACK_ANT1,
	HSADC_EVENT_RECAL_REQUESTED_ANT0_1,
	HSADC_EVENT_RECAL_REQ_ACK_ANT0_1,
	HSADC_EVENT_RECAL_REQ_DENIED,
	HSADC_EVENT_RECAL_COMPLETED,
	HSADC_EVENT_RECAL_COMPLETED2,
	HSADC_EVENT_RECAL_FAILED_ANT0,
	HSADC_EVENT_RECAL_FAILED_ANT1,
	HSADC_EVENT_RECAL_FAILED_ANT0_1,
	DCS_EVENT_MAX,
};

struct dcs_if {
	enum dcs_eventID eventid;
	uint32_t pL1_cbk_fn;
} __attribute__ ((packed));

#define GUL_CLI_MSG_ID_GENERIC 0
#define GUL_CLI_MSG_ID_L1REFAPP 1
#define GUL_CLI_MSG_ID_MAX GUL_CLI_MSG_ID_L1REFAPP

struct cli_mbox {
	uint32_t msg_id;
	uint32_t data;
	uint32_t data2;
	uint32_t data3;
} __attribute__ ((packed));


/* XXX:NOTE: Always increment HIF version when you add anything in
 * struct gul_hif. Following are rules for MAJOR/MINOR increment
 * MAJOR version: If a new register/register group is added.
 * MINOR version: If a new bit/flag of a register is added.
 */

#define GUL_HIF_MAJOR_VERSION		(1)
#define GUL_HIF_MINOR_VERSION		(1)
#define MSI_IRQ_COUNT 8

struct hif_msi_regs {
	uint32_t msi_addr_off_l;
	uint32_t msi_addr_off_h;
	uint32_t msi_val;
} __attribute__((packed));

enum tbgen_clk_source {
	NO_SRC = 0,
	HS_DCS_OUTPUT,
	LS_DCS_OUTPUT,
	IPG_CLK,
};

struct tbgen_clock_info {
	uint32_t tbgen1_freq_khz;
	uint32_t tbgen2_freq_khz;
	enum tbgen_clk_source tbgen1_clk_src;
	enum tbgen_clk_source tbgen2_clk_src;
} __attribute__((packed));

struct gul_warmup_info{
	int32_t warmup_temp; /*Threshold warmup temp*/
	int32_t warmup_current_temp; /*Current geul temp*/
	uint32_t warmup_timeout; /*warm-up timeout val*/
	uint32_t warmup_poll_intvl; /*interval val for logging current temp*/
	uint32_t warmup_flags; /*Current modem state value during warmup.
				 val = 0x8000_0000 during normal_boot = 0x0*/
};

struct gul_hif {
	uint32_t ver;
	uint32_t hif_ver;
	uint32_t soc_rev;
	uint32_t soc_numcores;
	uint32_t host_board_rev;
	uint32_t status;
	volatile uint32_t host_ready;
	volatile uint32_t mod_ready;
	uint32_t modem_share_area_size;
	uint32_t modem_host_data_size;
	uint32_t modem_rf_data_size;
	struct host_mem_region host_regions[HOST_MEM_END];
	struct irq_evt_regs irq_evt_regs;
	struct debug_log_regs dbg_log_regs[GUL_EP_CORE_MAX];
	uint32_t ulLogIndex[GUL_EP_CORE_MAX];
	struct gul_stats stats;
	struct hif_ipc_regs ipc_regs;
	struct hif_rfic_regs rfic_regs;
	struct hif_msi_regs msi_regs[MSI_IRQ_COUNT];
	struct host_msi_unit hmsi_unit[HOST_MSI_MAX_IRQ_COUNT];
	struct rf_host_if rf_hif;
	struct hawk_host_if hawk_hif;
	uint32_t msi_mtd_tvd;
	uint32_t msi_mtd_tvd_curentTemp;
	uint32_t msi_rtd_tvd_curentTemp;
	uint32_t msi_mtd_power_info;
	union  mtdcurentTemp mtd_curentTemp;
	union mtdpowerInfo mtd_power_info;
	uint32_t rtd_curentTemp;
	uint32_t mtd_hysteresisVal;
	struct mtd_thermalEvent mtdThermalEvent;
	struct rtd_thermalEvent rtdThermalEvent;
	struct tvd_mtd_threshold mtd_threshold;
	struct tvd_rtd_threshold rtd_threshold;
	enum tvd_mtdEventId tvd_mtdEvent;
	enum tvd_rtdEventId tvd_rtdEvent;
	enum tvd_mtdPowerEventId tvd_mtdPowerEvent;
	struct cli_mbox cli_geul_mbox;
	struct cli_mbox cli_host_mbox;
	uint32_t msi_cli;
	uint32_t ls_dac_sps;
	uint32_t ls_adc_sps;
	uint32_t hsdcs_sps;
	struct tbgen_clock_info tbgen_clk_info;
	struct gul_warmup_info warmup_info;
	struct dcs_if dcshif;
	uint32_t msi_dcs;
	uint32_t core_status_flag;
	uint32_t lsdac_mask;
	uint32_t lsadc_mask;
	uint32_t modem_host_uart;
	uint32_t disable_sideband;
	uint32_t msi_tti;
	uint32_t pcie2_link;
} __attribute__((packed));

#define GUL_VER_MAJOR(ver) ((ver >> 16) & 0xffff)
#define GUL_VER_MINOR(ver) (ver & 0xffff)
#define GUL_VER_MAKE(major, minor) (((major & 0xffff) << 16) \
				| (minor & 0xffff))

/* Host Ready bits */
#define HIF_HOST_READY_HOST_REGIONS	(1 << 0)
#define HIF_HOST_READY_VSPA1		(1 << 3)
#define HIF_HOST_READY_VSPA2		(1 << 4)
#define HIF_HOST_READY_VSPA3		(1 << 5)
#define HIF_HOST_READY_VSPA4		(1 << 6)
#define HIF_HOST_READY_VSPA5		(1 << 7)
#define HIF_HOST_READY_VSPA6		(1 << 8)
#define HIF_HOST_READY_VSPA7		(1 << 9)
#define HIF_HOST_READY_VSPA8		(1 << 10)
#define HIF_HOST_READY_RFIC		(1 << 11)
#define HIF_HOST_READY_IPC_LIB		(1 << 12)
#define HIF_HOST_READY_IPC_APP		(1 << 13)
#define HIF_HOST_READY_FECA		(1 << 14)
#define HIF_HOST_READY_DCS_HS		(1 << 15)
#define HIF_HOST_READY_DCS_LS		(1 << 16)
#define HIF_HOST_READY_RFIC2		(1 << 17)
#define HIF_HOST_READY_LOGGER		(1 << 18)
#define HIF_HOST_READY_HS_TBGEN2 	(1 << 19)
#define HIF_HOST_DISABLE_TBGEN2 	(1 << 20)
#define HIF_HOST_PROBE_COMPLETE 	(1 << 21)


/* ls dcs_clk is 491.52MHz */
/* divisor 1, sps: 491.52 MHz */
#define LS_DAC_SPS_491 491
/* divisor 2, sps: 245.76 MHz */
#define LS_DAC_SPS_245 245
/* divisor 4, sps:  122.88 MHz */
#define LS_DAC_SPS_122 122
/* divisor 8, sps: 61.44 MHz */
#define LS_DAC_SPS_61  61
/* divisor 2, sps: 245.76 MHz */
#define LS_ADC_SPS_245 245
/* divisor 4, sps:  122.88 MHz */
#define LS_ADC_SPS_122 122
/* divisor 8, sps: 61.44 MHz */
#define LS_ADC_SPS_61  61
/* divisor 16, sps: 30.72 MHz */
#define LS_ADC_SPS_30  30

#define HSDCS_SPS_1966 1966
#define HSDCS_SPS_983  983

/* Host will set flags in BE for Modem */
#ifdef __KERNEL__
#define SET_HIF_HOST_RDY(hif, RDY_MASK) (iowrite32be((ioread32be(&hif->host_ready) | RDY_MASK), &hif->host_ready))
#define CHK_HIF_MOD_RDY(hif, RDY_MASK) (ioread32be(&hif->mod_ready) & RDY_MASK)
#else
/* For application/dpdk */
#define SET_HIF_HOST_RDY(hif, RDY_MASK) (hif->host_ready = htobe32(be32toh(hif->host_ready) | RDY_MASK))
#define CHK_HIF_MOD_RDY(hif, RDY_MASK) (be32toh(hif->mod_ready) & RDY_MASK)
#endif /* __KERNEL__ */

#ifdef MODEM
#define SET_HIF_MOD_RDY(hif, RDY_MASK)  (hif->mod_ready |= RDY_MASK)
#define CHK_HIF_HOST_RDY(hif, RDY_MASK) ((hif->host_ready) & RDY_MASK)
#endif /* MODEM */


/* Modem Ready bits */
#define HIF_MOD_READY_AIOP_ATUS		(1 << 0)
#define HIF_MOD_READY_IPC_LIB		(1 << 5)
#define HIF_MOD_READY_IPC_APP		(1 << 6)
#define HIF_MOD_READY_FECA		(1 << 7)
#define HIF_MOD_READY_RFIC		(1 << 8)
#define HIF_MOD_READY_HAWK		(1 << 9)

/* Set IRQ_REAL_MSI_BIT to enable dedicated MSI interrupt line ,
 * and virtual irq line can be used by setting the TEST or LAST
 * EVT bits */

typedef enum {
	IRQ_EVT_IPC_CH1_BIT = 0,
	IRQ_EVT_IPC_CH2_BIT,
	IRQ_EVT_IPC_CH3_BIT,
	IRQ_EVT_IPC_CH4_BIT,
	IRQ_EVT_VSPA_BIT,
	IRQ_EVT_TEST_BIT,
	IRQ_EVT_LAST_BIT,
	IRQ_REAL_MSI_BIT
} gul_irq_evt_bits_t;


#define GUL_IRQ_EVT(bit) (1 << bit)
#define GUL_EVT_BTS_PER_WRD	32

/* XXX:NOTE: If you add an EVT in gul_irq_evt_bits_t, add the bit
 * in relevant mask below as well. If you add new Event group in additional to
 * the groups (VSPA, IPC, TEST) below. Define a new mask and add handling
 * in gul_get_subdrv_virqmap() function
 */
#define IRQ_EVT_VSPA_EVT_MASK	(GUL_IRQ_EVT(IRQ_EVT_VSPA_BIT))
#define IRQ_EVT_IPC_EVT_MASK	(GUL_IRQ_EVT(IRQ_EVT_IPC_CH1_BIT) |	\
				 GUL_IRQ_EVT(IRQ_EVT_IPC_CH2_BIT) |	\
				 GUL_IRQ_EVT(IRQ_EVT_IPC_CH3_BIT) |	\
				 GUL_IRQ_EVT(IRQ_EVT_IPC_CH4_BIT))
#define IRQ_EVT_TEST_EVT_MASK	(GUL_IRQ_EVT(IRQ_EVT_TEST_BIT))
#define IRQ_EVT_MSI_MASK	(GUL_IRQ_EVT(IRQ_REAL_MSI_BIT))

#ifdef MODEM
#pragma pack(pop)
#endif
#endif