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rfic_defs.h
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163 lines (148 loc) · 5.85 KB
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/*
* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
* Copyright 2020-2022 NXP
*/
#ifndef __RFIC_DEFS_H__
#define __RFIC_DEFS_H__
#define I2C_WRITE_DATA_LOW_BYTE (0x4d)
#define I2C_CONTROL (0x4a)
#define SPI_LENGTH (0x2)
#define SPI_CHAIN_NO_TX_0 (0 << 4)
#define SPI_CHAIN_NO_TX_1 (1 << 4)
#define SPI_CHAIN_NO_TX_2 (2 << 4)
#define SPI_CHAIN_NO_TX_3 (3 << 4)
#define SPI_CHAIN_NO_RX_0 (4 << 4)
#define SPI_CHAIN_NO_RX_1 (5 << 4)
#define SPI_CHAIN_NO_TX_M (6 << 4)
#define SPI_CHAIN_NO_RX_M (7 << 4)
#define SPI_CHAIN_PLL_CHIP (8 << 4)
#define SPI_WRITE_CHAIN_MASK (0xFF)
#define SPI_MV2801_CHAIN_0 (1 << 0)
#define SPI_MV2801_CHAIN_1 (1 << 1)
#define SPI_MV2801_CHAIN_2 (1 << 2)
#define SPI_MV2801_CHAIN_3 (1 << 3)
#define SPI_MV2802_CHAIN_0 (1 << 4)
#define SPI_MV2802_CHAIN_1 (1 << 5)
#define SPI_MV2803_TX (1 << 6)
#define SPI_MV2803_RX (1 << 7)
#define SPI_CHAIN_LOCATION_TX_FE (0xF)
#define SPI_CHAIN_LOCATION_RX_FE (0xF)
#define SPI_CHAIN_LOCATION_TX_MIX (0xF)
#define SPI_CHAIN_LOCATION_RX_MIX (0x3)
#define SPI_CHAIN_LOCATION_PLL (0x1)
#define SPI_CONFIG_FAST_WRITE_SPI_MASTER (0 << 3)
#define SPI_CONFIG_SERIAL_PORT (1 << 3)
#define SPI_CLK_ENABLE (1 << 7)
#define SPI_CLK_DISABLE (0 << 7)
#define SEQ_CMD_LENGTH (0x0)
#define SPI_RESET (0x0)
#define TX_RX_INDEX_RAM_ADDR (0x0)
#define AGC_BEAM1_ENABLE (1 << 0)
#define AGC_BEAM2_ENABLE (1 << 1)
#define TX_PBK_INDEX_NO_RESET (0 << 2)
#define TX_PBK_INDEX_RESET (1 << 2)
#define TX_PBK_ADDR_BY_INDEX_REGISTER (0 << 1)
#define TX_PBK_ADDR_BY_INDEX_COUNTER (1 << 1)
#define TX_PBK_INDEX_COUNTER_INC_RISING_EDGE (0 << 0)
#define TX_PBK_INDEX_COUNTER_INC_PBK_DELAY_CLK_CYCLES (1 << 0)
#define TX_BBK_RAM_FUNC_MODE (0 << 3)
#define TX_BBK_RAM_SPI_ACCESS (1 << 3)
#define TX_BBK_RAM_ADDR_BY_INDEX_REGISTER (0 << 2)
#define TX_BBK_RAM_ADDR_BY_PBK_OUTPUT (1 << 2)
#define TX_BBK_UPDATE_RISING_EDGE (0 << 1)
#define TX_BBK_UPDATE_BBK_RAM_OUTPUT (1 << 1)
#define TX_BBK_RAM_COEFF_SEL_PHASE_INDEX_COEFF (0 << 0)
#define TX_BBK_RAM_COEFF_SEL_BBK_RAM_OUTPUT (1 << 0)
#define RX_PBK_INDEX_NO_RESET (0 << 2)
#define RX_PBK_INDEX_RESET (1 << 2)
#define RX_PBK_ADDR_BY_INDEX_REGISTER (0 << 1)
#define RX_PBK_ADDR_BY_INDEX_COUNTER (1 << 1)
#define RX_PBK_INDEX_COUNTER_INC_RISING_EDGE (0 << 0)
#define RX_PBK_INDEX_COUNTER_INC_PBK_DELAY_CLK_CYCLES (1 << 0)
#define RX_BBK_RAM_FUNC_MODE (0 << 3)
#define RX_BBK_RAM_SPI_ACCESS (1 << 3)
#define RX_BBK_RAM_ADDR_BY_INDEX_REGISTER (0 << 2)
#define RX_BBK_RAM_ADDR_BY_PBK_OUTPUT (1 << 2)
#define RX_BBK_UPDATE_RISING_EDGE (0 << 1)
#define RX_BBK_UPDATE_BBK_RAM_OUTPUT (1 << 1)
#define RX_BBK_RAM_COEFF_SEL_PHASE_INDEX_COEFF (0 << 0)
#define RX_BBK_RAM_COEFF_SEL_BBK_RAM_OUTPUT (1 << 0)
#define AGC_AUTO_FIXED_WRITE_MODE_ENABLE (1 << 6)
#define RX_PLL_AUTO_CAP_ENABLE (1 << 0)
#define RX_SPI_SLOT_HIGH_ENABLE (1 << 2)
#define RX_SPI_SLOT_LOW_ENABLE (1 << 3)
#define TX_SPI_SLOT_HIGH_ENABLE (1 << 4)
#define TX_SPI_SLOT_LOW_ENABLE (1 << 5)
#define RX_SPI_SLOT_ENABLE (RX_SPI_SLOT_HIGH_ENABLE | \
RX_SPI_SLOT_LOW_ENABLE)
#define TX_SPI_SLOT_ENABLE (TX_SPI_SLOT_HIGH_ENABLE | \
TX_SPI_SLOT_LOW_ENABLE)
#define SPI_SLOTS_MASK (RX_SPI_SLOT_ENABLE | \
TX_SPI_SLOT_ENABLE)
#define RX_GPIO_AGC_INDEX_UPDATE_ENABLE (1 << 6)
#define LOGEN_CAL_0_ENABLE (1 << 0)
#define LOGEN_CAL_1_ENABLE (1 << 1)
#define LOGEN_CAL_ENABLE (LOGEN_CAL_0_ENABLE | \
LOGEN_CAL_1_ENABLE)
#define LOGEN_SELECT_BEAM1 (0x0)
#define LOGEN_SELECT_BEAM2 (0x3)
/* 2801 REGS */
#define TX_2801_RAM_ADDR_REG (0x33)
#define TX_2801_BBK_INDEX_REG (0x38)
#define TX_2801_PBK_CONTROL_1_REG (0x34)
#define TX_2801_BBK_CONTROL_1_REG (0x37)
#define TX_2801_PBK_REGION_BBK_INDEX_REG (0x120)
/* 2802 REGS */
#define RX_2802_RAM_ADDR_REG (0x2C)
#define RX_2802_BBK_INDEX_REG (0x31)
#define RX_2802_PBK_CONTROL_1_REG (0x2D)
#define RX_2802_BBK_CONTROL_1_REG (0x30)
#define RX_2802_PBK_REGION_BBK_INDEX_REG (0x120)
/* 2803 REGS */
#define MIXER_BG_2_REG (0x5)
#define MIXER_BG_3_REG (0x6)
#define MIXER_RD_TEMP_CONTROL_REG (0xCA)
#define MIXER_RD_TEMP_DELAY_REG (0xCB)
#define MIXER_RD_TEMP_VALUE_REG (0xCC)
#define MIXER_TX_LOGEN_ITBB_PPF1_REG (0x159)
#define MIXER_TX_LOGEN_ITBB_PPF2_REG (0x15A)
#define MIXER_RX_LOGEN_ITBB_PPF1_REG (0x157)
#define MIXER_RX_LOGEN_ITBB_PPF2_REG (0x158)
/* 2804 REGS */
#define PLL_2804_LF_10_REG (0x14)
/* FPGA REGS */
#define FPGA_SPI_WRITE_CHAIN_MASK_REG (0x02)
#define FPGA_SPI_CMD_REG (0x10)
#define FPGA_SPI_CHAIN_NO_REG (0x11)
#define FPGA_SPI_CHAIN_LOC_REG (0x12)
#define FPGA_SPI_CONFIG_MODE_REG (0x13)
#define FPGA_TX_SEQ_ST_INDEX_REG (0x2A)
#define FPGA_TX_SEQ_END_INDEX_REG (0x2B)
#define FPGA_INDEX_RAM_ADDR_REG (0x2C)
#define FPGA_TX_INDEX_RAM_WDATA_LSB_REG (0x2D)
#define FPGA_TX_INDEX_RAM_WDATA_MSB_REG (0x2E)
#define FPGA_PLL_AUTO_CAP_LOW_HIGH_REG (0xC4)
#define FPGA_PLL_AUTO_CAP_VAL_LSB_REG (0xC5)
#define FPGA_PLL_AUTO_CAP_VAL_MSB_REG (0xC6)
#define FPGA_RX_INDEX_RAM_WDATA_LSB_REG (0x41)
#define FPGA_RX_INDEX_RAM_WDATA_MSB_REG (0x42)
#define FPGA_TX_RX_SEQ_STATUS_REG (0x44)
#define FPGA_TX_RISING_EDGE_SEQ_NO_REG (0x9E)
#define FPGA_TX_FALLING_EDGE_SEQ_NO_REG (0x9F)
#define FPGA_RX_RISING_EDGE_SEQ_NO_REG (0xA0)
#define FPGA_RX_FALLING_EDGE_SEQ_NO_REG (0xA1)
#define FPGA_AGC_INDEX_CONTROL_REG (0xA2)
#define FPGA_RX_PLL_AGC_ENABLE_REG (0xBE)
#define FPGA_LOGEN_CAL_REG (0xBF)
#define FPGA_AGC_BEAM_SELECT_REG (0xD7)
#define FPGA_SPI_QUEUE_RESET_REG (0xCA)
#define FPGA_TX_SPI_QUEUE_READ_REG (0xCD)
#define FPGA_PEND_TX_SPI_WRITE_REG (0xCE)
#define FPGA_PEND_TX_SPI_READ_REG (0xCF)
#define FPGA_TX_SPI_READ_COUNT_REG (0xD0)
#define FPGA_RX_SPI_QUEUE_READ_REG (0xD8)
#define FPGA_PEND_RX_SPI_WRITE_REG (0xD9)
#define FPGA_PEND_RX_SPI_READ_REG (0xDA)
#define FPGA_RX_SPI_READ_COUNT_REG (0xDB)
#define FPGA_LOGEN_SELECT_BEAM_REG (0xD1)
#endif /* __RFIC_DEFS_H__ */