geul_common_headers/rfic_sw_cmdq.h at oss · nxp-qoriq/geul_common_headers · GitHub

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/*
 * SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
 * Copyright 2020, 2022 NXP
 *
 */
#ifndef __RFIC_SW_CMDQ_H__
#define __RFIC_SW_CMDQ_H__
#pragma pack(push, 1)

#include "rfic_common.h"
#include "rf_sw_cmds.h"

#define RFIC_SWCMD_DATA_SIZE    68
#define MAX_REGS 32
#define RFIC_CMD_TIMEOUT	20

typedef enum rfic_sw_cmd {
	RFIC_SWCMD_INVALID,
	RFIC_SWCMD_READ_REG,
	RFIC_SWCMD_WRITE_REG,
	RFIC_SWCMD_MIXED_REG,
	RFIC_SWCMD_SET_BB_INDEX_TX,
	RFIC_SWCMD_SET_BB_INDEX_RX,
	RFIC_SWCMD_WRITE_LIST_TO_PBK_MEMORY_TX,
	RFIC_SWCMD_WRITE_LIST_TO_PBK_MEMORY_RX,
	RFIC_SWCMD_SET_PBK_MODE_TX,
	RFIC_SWCMD_SET_PBK_MODE_RX,
	RFIC_SWCMD_PLL_CAP_CORRECTION,
	RFIC_SWCMD_GET_PLL_LOCK_STATUS,
} rfic_sw_cmd_t;

typedef enum rfic_status {
	RFIC_STS_NO_ISSUE = 0,
	RFIC_STS_ERROR
} rfic_status_t;

typedef enum rfic_op {
	RFIC_OP_READ_REG,
	RFIC_OP_WRITE_REG,
	RFIC_OP_POLL_REG,
	RFIC_OP_READ_OR_WRITE_REG,
	RFIC_OP_READ_AND_WRITE_REG,
	RFIC_OP_WAIT_FOR_MASK
} rfic_op_t;

struct rfic_sw_cmdq_cmd {
	uint32_t cmd;
	uint32_t flags;
	uint32_t status;
	uint32_t data[RFIC_SWCMD_DATA_SIZE];
};

struct rfic_common_mdata {
	struct rfic_sw_cmdq_cmd host_swcmd;
	uint32_t state;
	uint32_t host_swcmd_status;
};

struct sw_cmddata_reg_rw {
	uint32_t count;
	struct rfic_reg_rw rfic_reg_rw[MAX_REGS];
};

struct sw_cmddata_mixed_reg {
	rfic_op_t op;
	struct rfic_reg_rw rfic_reg_rw;
};

struct sw_cmddata_seq_reg {
	uint32_t count;
	struct sw_cmddata_mixed_reg sw_cmddata_mixed[MAX_MIX_REGS];
};

#pragma pack(pop)
#endif