yuc_rfic_common.h

/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
 * Copyright 2020-2022 NXP
 *
 */
#ifndef __YUC_RFIC_COMMON_H__
#define __YUC_RFIC_COMMON_H__

#include <yuc_rfic_types.h>

/* Each command has command spefic data, defined
 * by sw_cmd_* structs as given below.
 *
 * NOTE:XXX: The size of these structs should not exceed
 * RFIC_SWCMD_DATA_SIZE 32 bit words,if it does then please
 * change RFIC_SWCMD_DATA_SIZE macro to required size
 */

typedef struct sw_cmd_setget_path
{
    uint32_t rtc;
    uint32_t path;
    uint32_t band;
    uint32_t mode;
    uint32_t rssi_mode;
    uint32_t dpd;
    uint32_t rxbw;
    uint32_t txbw;
} __attribute__( ( packed ) ) sw_cmd_setget_path_t;

typedef struct sw_cmd_setget_calpll
{
    uint32_t rtc;
    uint32_t mode;
    uint32_t freq_khz;
    uint32_t cal_band;
} __attribute__( ( packed ) ) sw_cmd_setget_calpll_t;

typedef struct sw_cmd_set_gain
{
    uint32_t path;
    uint32_t manual;
    uint32_t channel;
    uint32_t hash_mode;
    uint32_t bb_gain;
    uint32_t rf_gain;
    uint32_t tx_gain;
    uint32_t rx_gain;
} __attribute__( ( packed ) ) sw_cmd_set_gain_t;

typedef struct sw_cmd_get_gain
{
    uint32_t rtc;
    uint32_t rx1_manual;
    uint32_t rx1_hash_mode;
    uint32_t channel;
    uint32_t rx1_gain;
    uint32_t rx1_bbgain;
    uint32_t rx1_rfgain;
    uint32_t rx2_manual;
    uint32_t rx2_hash_mode;
    uint32_t rx2_gain;
    uint32_t rx2_bbgain;
    uint32_t rx2_rfgain;
    uint32_t tx1_gain;
    uint32_t tx2_gain;
    uint32_t rx1_gain_raw;
    uint32_t rx2_gain_raw;
    uint32_t tx1_gain_raw;
    uint32_t tx2_gain_raw;
    uint32_t tx_gain_idx;
    uint32_t rx_gain_idx;
} __attribute__( ( packed ) ) sw_cmd_get_gain_t;

typedef struct sw_cmd_set_bbloopback
{
    uint32_t rtc;
    uint32_t rx;
    uint32_t txbw;
    uint32_t rxbw;
} __attribute__( ( packed ) ) sw_cmd_set_bbloopback_t;

typedef struct sw_cmd_set_rfloopback
{
    uint32_t rtc;
    uint32_t rx;
    uint32_t band;
    uint32_t loop_mode;
} __attribute__( ( packed ) ) sw_cmd_set_rfloopback_t;

typedef struct sw_cmd_setget_rxdc
{
    uint32_t rtc;
    uint32_t rx;
    uint32_t channel;
    uint32_t iq_select;
    int32_t fine0;
    int32_t coarse0;
    int32_t fine1;
    int32_t coarse1;
    int32_t fine2;
    int32_t coarse2;
    int32_t fine3;
    int32_t coarse3;
    int32_t fine4;
    int32_t coarse4;
    int32_t fine5;
    int32_t coarse5;
    int32_t fine6;
    int32_t coarse6;
    int32_t fine7;
    int32_t coarse7;
} __attribute__( ( packed ) ) sw_cmd_setget_rxdc_t;

typedef struct sw_cmd_get_version
{
    uint32_t rtc;
    uint32_t hw_ver;
    uint32_t min_ver;
    uint32_t maj_ver;
    uint32_t tgt_ver;
    uint32_t bld_nr;
    uint32_t test_nr;
    uint32_t dbg_flg;
} __attribute__( ( packed ) ) sw_cmd_get_vers_t;

typedef struct sw_cmd_get_sys_status
{
    uint32_t rtc;
    uint32_t sys_state;
    uint32_t trxpll_vco_det_lo;
    uint32_t trxpll_vco_det_hi;
    uint32_t trxpll_vtune_det_lo;
    uint32_t trxpll_vtune_det_hi;
    uint32_t trxpll_unlock;
    uint32_t calpll_vtune_det_lo;
    uint32_t calpll_vtune_det_hi;
    uint32_t calpll_unlock;
} __attribute__( ( packed ) ) sw_cmd_get_sys_status_t;

typedef struct sw_cmd_setget_property
{
    uint32_t rtc;
    uint32_t property_id;
    uint32_t length;
    uint32_t value1;
    uint32_t value2;
    uint32_t value3;
    uint32_t value4;
    uint32_t value5;
    uint32_t value6;
    uint32_t value7;
    uint32_t value8;
} __attribute__( ( packed ) ) sw_cmd_setget_property_t;

typedef struct sw_cmd_setactive
{
    uint32_t rtc;
    uint32_t mode;
    uint32_t dpd_rx;
} __attribute__( ( packed ) ) sw_cmd_setactive_t;

typedef struct sw_cmd_setcal_rxdc
{
    uint32_t rtc;
    uint32_t rx;
    uint32_t mode;
    int32_t ifine;
    int32_t icoarse;
    int32_t qfine;
    int32_t qcoarse;
} __attribute__( ( packed ) ) sw_cmd_setcal_rxdc_t;

typedef struct sw_cmd_setget_register
{
    uint32_t rtc;
    uint32_t addr;
    uint32_t length;
    uint32_t mask;
    uint32_t value1;
    uint32_t value2;
    uint32_t value3;
    uint32_t value4;
    uint32_t value5;
    uint32_t value6;
    uint32_t value7;
    uint32_t value8;
} __attribute__( ( packed ) ) sw_cmd_setget_register_t;

typedef struct sw_cmd_get_temperature
{
    uint32_t rtc;
    uint32_t temperature;
    uint32_t value_raw;
} __attribute__( ( packed ) ) sw_cmd_get_temperature_t;

typedef struct sw_cmd_setget_lnabypass_t
{
    uint32_t enable;
} __attribute__( ( packed ) ) sw_cmd_setget_lnabypass_t;

typedef struct sw_cmd_setget_dpdsw_t
{
    uint32_t enable;
} __attribute__( ( packed ) ) sw_cmd_setget_dpdsw_t;

typedef struct sw_cmd_setget_rssi
{
    uint32_t rtc;
    uint32_t receiver;
    uint32_t mode;
    uint32_t rate;
    uint32_t threshold;
    uint32_t ref_g0_0;
    uint32_t ref_g0_1;
    uint32_t ref_g0_2;
    uint32_t ref_g1_0;
    uint32_t ref_g1_1;
    uint32_t ref_g1_2;
    uint32_t ref_gother_0;
    uint32_t ref_gother_1;
    uint32_t ref_gother_2;
} __attribute__( ( packed ) ) sw_cmd_setget_rssi_t;

typedef struct yuc_pll_cal {
	/* TRX PLL */
	uint32_t cal_cap;
	uint32_t cal_current;
	uint32_t vco_sel;
}  __attribute__((packed)) yuc_pll_cal_t;

typedef struct yuc_IQ_dcoc {
	int32_t i_coarse;
	int32_t i_fine;
	int32_t q_coarse;
	int32_t q_fine;
}  __attribute__((packed)) yuc_IQ_dcoc_t;

typedef struct yuc_IQ_zgain_dc {
	int16_t Idc;
	int16_t Qdc;
}  __attribute__((packed)) yuc_IQ_zgain_dc_t;

typedef struct yuc_rxdc_gain_cal {
	yuc_IQ_dcoc_t gain_rxdc[YUC_RX_RF_GAIN_LEVELS];//8*16 =128
	yuc_IQ_dcoc_t gain_dpd_rxdc[YUC_RX_RF_GAIN_LEVELS];//128+8*16=256
	yuc_IQ_dcoc_t gain_calp_rxdc;//256+16=272
	yuc_IQ_zgain_dc_t rxdc_zgain;//272+4 =276
	yuc_IQ_zgain_dc_t dpd_rxdc_zgain;//=276+4=280
	yuc_IQ_zgain_dc_t calp_rxdc_zgain;//280+4=284
}  __attribute__((packed)) yuc_rxdc_gain_cal_t;

typedef struct yuc_rxdc_rx_cal {
	yuc_rxdc_gain_cal_t rx_rxdc[YUC_CAL_RXDC_RX_CNT];//2*284=568
}  __attribute__((packed)) yuc_rxdc_rx_cal_t;

typedef struct yuc_IQ_imb {
	uint32_t num_tones;//4
	int32_t gimb_arr[YUC_IQIMB_TONE_MAX_CNT];//4+8*4=36
	int32_t pimb_arr[YUC_IQIMB_TONE_MAX_CNT];//36+8*4=68
	int32_t mean_gimb;//68+4=72
	int32_t mean_pimb;//72+4=76
	int32_t cmp_dc_real[YUC_IQIMB_TONE_MAX_CNT];//76+8*4=108
	int32_t cmp_dc_imag[YUC_IQIMB_TONE_MAX_CNT];//108+8*4=140
	int32_t mean_cmp_dc_real;//140+4=144
	int32_t mean_cmp_dc_imag;//144+4=148
	int32_t skew;//148+4=152
}  __attribute__((packed)) yuc_IQ_imb_t;

typedef struct yuc_cal_data {
    uint32_t magic;
    uint32_t ver;/**< For checking compatility */
    uint32_t state;
    uint32_t recalib;
    /* calib data starts from here */
    int32_t vcxo_tune;//20
    yuc_pll_cal_t pll[YUC_CAL_PLL_FREQ_CNT];//20+4*12=68
    uint32_t tx_bw[YUC_CAL_TXBW_MAX];//68+2*4=76
    uint32_t rx_bw[YUC_CAL_RXBW_MAX];//76+10*4 = 116
    yuc_rxdc_rx_cal_t freq_rxdc[YUC_CAL_RXDC_FREQ_CNT];//116+4*568=116+2272 =2388
    /* Can add extra params below */
    yuc_IQ_imb_t rx_IQimb[YUC_IQIMB_RX_CNT];//2388+2*152=2692
    yuc_IQ_imb_t tx_IQimb[YUC_IQIMB_TX_CNT];//2692+2*152=2996
    /* Padding as caldata size is not aligned to 64bytes */
    uint32_t padding[3];//2996+3*4=3008
} __attribute__( ( packed ) ) yuc_cal_data_t;

#endif /* ifndef __YUC_RFIC_COMMON_H__ */