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compile and run vhdl
1 parent d1a5556 commit d189829

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‎.gitignore‎

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@@ -39,3 +39,7 @@ example.exe.dSYM/
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example.exe
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ipxact2systemverilog/ipxact2systemverilog.egg-info/
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*.o
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tb_vhd
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a.out

‎.vscode/extensions.json‎

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{
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"recommendations": ["esbenp.prettier-vscode", "mshr-h.veriloghdl"]
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}
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"recommendations": [
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"charliermarsh.ruff",
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"littlefoxteam.vscode-python-test-adapter",
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"streetsidesoftware.code-spell-checker",
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"eamodio.gitlens"
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],
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"unwantedRecommendations": [
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"ms-python.mypy-type-checker"
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]
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}

‎.vscode/settings.json‎

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{
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"cSpell.words": ["ipxact", "setuptools", "systemverilog", "venv", "vhdl"],
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"makefile.configureOnOpen": false,
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// Python settings
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"settings": {
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"osx": {
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"python.defaultInterpreterPath": "./venv/bin/python"
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},
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"linux": {
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"python.defaultInterpreterPath": "./venv/bin/python"
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},
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"windows": {
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"python.defaultInterpreterPath": ".\\venv\\Scripts\\python.exe"
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}
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},
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// Optional: let YOUR script handle env activation instead of the Python extension
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"python.terminal.activateEnvironment": false,
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// macOS: open zsh, source your script, then drop into a login shell
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"terminal.integrated.profiles.osx": {
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"Project (source_me)": {
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"path": "/bin/zsh",
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"args": ["-l", "-c", "source ${workspaceFolder}/source_me; exec zsh -l"],
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"env": {
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"PYTHONPATH": "${workspaceFolder}"
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}
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}
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},
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// Linux: open bash, source your script, then drop into a login shell
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"terminal.integrated.profiles.linux": {
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"Project (source_me)": {
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"path": "/bin/bash",
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"args": ["-l", "-c", "source ${workspaceFolder}/source_me; exec bash -l"],
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"env": {
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"PYTHONPATH": "${workspaceFolder}"
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}
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}
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},
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"terminal.integrated.defaultProfile.osx": "Project (source_me)",
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"terminal.integrated.defaultProfile.linux": "Project (source_me)",
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"pythonTestExplorer.testFramework": "pytest",
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// Pytest settings to show print output
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"python.testing.pytestArgs": ["-s", "-v"],
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"python.testing.unittestEnabled": false,
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"python.testing.pytestEnabled": true,
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// Editor settings
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"editor.formatOnSave": true,
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"editor.defaultFormatter": "esbenp.prettier-vscode"
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"editor.detectIndentation": true,
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"editor.rulers": [120],
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"editor.tabSize": 4,
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// File associations
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"files.associations": {
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"*.py": "python"
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},
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// Exclude patterns
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"files.exclude": {
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"**/__pycache__": true,
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"**/*.pyc": true,
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"**/.pytest_cache": true,
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"**/venv": false
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},
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// Search settings
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"search.exclude": {
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"**/__pycache__": true,
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"**/*.pyc": true,
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"**/venv": true,
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"**/.git": true
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},
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// Ruff integration for Python
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"[python]": {
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"editor.defaultFormatter": "charliermarsh.ruff",
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"editor.formatOnSave": true,
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"editor.codeActionsOnSave": {
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"source.fixAll.ruff": "explicit",
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"source.organizeImports.ruff": "explicit"
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}
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},
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// Disable MyPy type checking
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"python.analysis.typeCheckingMode": "off",
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"mypy-type-checker.args": [],
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// Terminal settings
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"terminal.integrated.env.osx": {
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"PYTHONPATH": "${workspaceFolder}"
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},
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"terminal.integrated.env.linux": {
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"PYTHONPATH": "${workspaceFolder}"
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},
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"terminal.integrated.env.windows": {
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"PYTHONPATH": "${workspaceFolder}"
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},
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// Extensions settings
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"extensions.disabled": {
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"ms-python.mypy-type-checker": true
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},
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"cSpell.words": [
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"endclass",
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"endfunction",
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"endinterface",
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"endmodule",
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"endtask",
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"ghdl",
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"iverilog",
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"posedge",
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"rstn",
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"verilator",
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"Verilog",
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"VHDL"
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],
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// Language-specific settings
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"[markdown]": {
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"editor.wordWrap": "off"
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},
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"[json]": {
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"editor.defaultFormatter": "esbenp.prettier-vscode"
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}
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}

‎Makefile‎

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XSD_DIR = schema1.5
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UNAME := $(shell uname)
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ifeq ($(UNAME), Linux)
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SVPARSER := ./tools/linux/depmapDebug
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else
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SVPARSER := ./tools/osx/slang-depmap
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endif
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all: gen
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vmake work > vmakefile
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compile_ghdl:
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ghdl -a example/output/*.vhd example/tb/vhd_dut.vhd
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ghdl -e vhd_dut
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ghdl -r vhd_dut
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ghdl -a --std=08 example/output/*.vhd example/tb/*.vhd
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ghdl -e --std=08 tb_vhd
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ghdl -r --std=08 tb_vhd
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test_c:
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gcc -Wall -g example/test/example.c -o example.exe
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compile_icarus:
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iverilog -g2012 -o foo example/output/*.sv
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parse_systemverilog:
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$(SVPARSER) example/output/
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.PHONY: whole_library example/output
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sim: whole_library
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clean:
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rm -rf work transcript vsim.wlf vmakefile vsim.dbg
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rm -rf vhd_dut *.o *.cf
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rm -rf a.out tb_sim obj_dir tb_icarus_sim tb_pkg_sim tb_sv_sim
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validate:
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xmllint --noout --schema ipxact2systemverilog/xml/ipxact-1.5/component.xsd example/input/test.xml

‎README.md‎

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available for Linux and Windows.
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```bash
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brew install pandoc
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brew install pandoc verilator ghdl
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# if you want to use sphinx
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brew install texlive

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