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tests: add tests for untested flows and flow-API tools
Add tests using the golden-file harness for the previously untested flow-API tools ghdl, sv2v, vpr, icetime and sandpipersaas, and for the previously untested flows icestorm, vivado, vpr, gowin and efinity. The flow test fixture gains a paramtypes argument (defaulting to the previous behaviour) since the gowin flow rejects vlogparam/vlogdefine parameters. The f4pga flow is left untested since its configure_flow still returns the legacy list-of-tuples flow description, which the current Edaflow base class cannot consume.
1 parent 6c1afd6 commit e8feae4

38 files changed

Lines changed: 1059 additions & 1 deletion

‎tests/edalize_flow_common.py‎

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Original file line numberDiff line numberDiff line change
@@ -49,9 +49,15 @@ def _flow_fixture(
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toplevel="top_module",
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ref_subdir="",
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config_files=[],
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paramtypes=["plusarg", "vlogdefine", "vlogparam"],
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):
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edam = get_edam(flow_options=flow_options, files=files, toplevel=toplevel)
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edam = get_edam(
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flow_options=flow_options,
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files=files,
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toplevel=toplevel,
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paramtypes=paramtypes,
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)
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ff = FlowFixture(flow_name, edam, tmp_path, ref_subdir)
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# ff.flow.work_root = tmp_path

‎tests/flows/efinity/Makefile‎

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#Auto generated by Edalize
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all: post_build
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pre_build:
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outflow/design.bit: sdc_file sv_file.sv vlog_file.v vlog_with_define.v vlog05_file.v vlog_incfile vhdl_file.vhd vhdl_lfile vhdl2008_file another_sv_file.sv | pre_build
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$(EDALIZE_LAUNCHER) env EFXPT_HOME=path/to/efinity/intallation/pt EFXPGM_HOME=path/to/efinity/intallation/pgm path/to/efinity/intallation/bin/python3 path/to/efinity/intallation/scripts/efx_run.py --prj design.xml --flow compile
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post_build: outflow/design.bit
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pre_run:
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run: pre_run
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post_run: run

‎tests/flows/efinity/design.xml‎

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<?xml version="1.0" encoding="UTF-8"?>
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<efx:project name="design" description="" last_change_date="" location="" sw_version="" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
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<efx:device_info>
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<efx:family name="Trion"/><efx:device name="T8F81"/><efx:timing_model name="C2"/> </efx:device_info>
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<efx:design_info def_veri_version="verilog_2k" def_vhdl_version="vhdl_2008">
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<efx:top_module name="top_module"/> <efx:design_file name="sv_file.sv" version="sv_09"/>
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<efx:design_file name="vlog_file.v" version=""/>
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<efx:design_file name="vlog_with_define.v" version=""/>
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<efx:design_file name="vlog05_file.v" version=""/>
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<efx:design_file name="vlog_incfile" version=""/>
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<efx:design_file name="vhdl_file.vhd" version=""/>
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<efx:design_file name="vhdl_lfile" version=""/>
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<efx:design_file name="vhdl2008_file" version=""/>
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<efx:design_file name="another_sv_file.sv" version="sv_09"/>
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<efx:top_vhdl_arch name=""/>
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</efx:design_info>
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<efx:package_info>
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<efx:package name=""/>
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</efx:package_info>
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<efx:constraint_info>
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<efx:sdc_file name="sdc_file" />
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</efx:constraint_info>
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<efx:sim_info/>
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<efx:misc_info/>
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<efx:ip_info/>
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<efx:synthesis tool_name="efx_map">
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<efx:param name="work_dir" value="work_syn" value_type="e_string"/>
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<efx:param name="write_efx_verilog" value="on" value_type="e_bool"/>
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<efx:param name="seq_opt" value="0" value_type="e_option"/>
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<efx:dynparam name="vlogparam_bool" value="True"/>
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<efx:dynparam name="vlogparam_int" value="42"/>
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<efx:dynparam name="vlogparam_str" value="hello"/>
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<efx:defmacro name="vlogdefine_bool" value="True"/>
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<efx:defmacro name="vlogdefine_int" value="42"/>
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<efx:defmacro name="vlogdefine_str" value="hello"/>
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</efx:synthesis>
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<efx:place_and_route tool_name="efx_pnr">
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<efx:param name="work_dir" value="work_pnr" value_type="e_string" />
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<efx:param name="verbose" value="off" value_type="e_bool" />
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<efx:param name="load_delaym" value="on" value_type="e_bool"/>
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</efx:place_and_route>
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<efx:bitstream_generation tool_name="efx_pgm">
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<efx:param name="mode" value="active" value_type="e_string"/>
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<efx:param name="width" value="1" value_type="e_string"/>
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<!-- on, off, smart -->
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<efx:param name="enable_roms" value="smart" value_type="e_option"/>
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<efx:param name="spi_low_power_mode" value="on" value_type="e_bool"/>
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<efx:param name="io_weak_pullup" value="on" value_type="e_bool"/>
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<efx:param name="oscillator_clock_divider" value="DIV8" value_type="e_option"/>
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<!-- on, off -->
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<efx:param name="bitstream_compression" value="on" value_type="e_bool"/>
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<!-- on, off -->
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<efx:param name="enable_external_master_clock" value="off" value_type="e_bool"/>
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<!-- posedge, negedge -->
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<efx:param name="active_capture_clk_edge" value="posedge" value_type="e_option"/>
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<efx:param name="jtag_usercode" value="0xFFFFFFFF" value_type="e_string"/>
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<!-- on, off -->
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<efx:param name="release_tri_then_reset" value="on" value_type="e_bool"/>
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</efx:bitstream_generation>
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<efx:debugger>
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<efx:param name="work_dir" value="work_dbg" value_type="e_string" />
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<efx:param name="auto_instantiation" value="off" value_type="e_bool" />
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<efx:param name="profile" value="NONE" value_type="e_string" />
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</efx:debugger>
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<efx:security>
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<!-- on, off -->
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<efx:param name="randomize_iv_value" value="on" value_type="e_bool"/>
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<efx:param name="iv_value" value="" value_type="e_string"/>
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</efx:security>
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</efx:project>

‎tests/flows/gowin/Makefile‎

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#Auto generated by Edalize
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all: post_build
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pre_build:
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pnr/design.fs: sdc_file sv_file.sv tcl_file.tcl vlog_file.v vlog_with_define.v vlog_incfile vhdl_file.vhd vhdl_lfile another_sv_file.sv | pre_build
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$(EDALIZE_LAUNCHER) gw_sh edalize_gowin_template.tcl
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post_build: pnr/design.fs
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pre_run:
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run: pre_run
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post_run: run

‎tests/flows/gowin/edalize_gowin_template.tcl‎

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set_device GW1NR-LV9QN88PC6/I5
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add_file -type sdc "sdc_file"
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add_file -type verilog "sv_file.sv"
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source tcl_file.tcl
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add_file -type verilog "vlog_file.v"
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add_file -type verilog "vlog_with_define.v"
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add_file -type verilog "vlog_incfile"
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add_file -type VHDL_FILE "vhdl_file.vhd"
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add_file -type VHDL_FILE "vhdl_lfile"
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set_file_prop -lib libx "vhdl_lfile"
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add_file -type verilog "another_sv_file.sv"
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set_option -top_module top_module
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set_option -vhdl_std vhd2008
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set_option -verilog_std sysv2017
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run syn
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run pnr

‎tests/flows/icestorm/Makefile‎

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#Auto generated by Edalize
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all: post_build
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synth: design.json
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bitstream: design.bin
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pre_build:
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design.json: edalize_yosys_template.tcl sv_file.sv tcl_file.tcl vlog_file.v vlog_with_define.v vlog05_file.v vlog_incfile another_sv_file.sv | pre_build
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$(EDALIZE_LAUNCHER) yosys -l yosys.log -p 'tcl edalize_yosys_template.tcl'
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design.asc: design.json
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$(EDALIZE_LAUNCHER) nextpnr-ice40 -l next.log --pcf pcf_file.pcf --json design.json --asc design.asc
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build-gui: design.json
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$(EDALIZE_LAUNCHER) nextpnr-ice40 -l next.log --pcf pcf_file.pcf --json design.json --asc design.asc --gui
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design.bin: design.asc
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$(EDALIZE_LAUNCHER) icepack design.asc design.bin
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design.tim: design.asc
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$(EDALIZE_LAUNCHER) icetime -r design.tim design.asc
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timing: design.tim
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design.stat: design.asc
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$(EDALIZE_LAUNCHER) icebox_stat design.asc design.stat
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stats: design.stat
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post_build: bitstream
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pre_run:
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run: pre_run
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post_run: run

‎tests/flows/vivado/Makefile‎

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#Auto generated by Edalize
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all: post_build
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pre_build:
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design.xpr design.xpr.marker: design.tcl sdc_file sv_file.sv tcl_file.tcl vlog_file.v vlog_with_define.v vlog05_file.v vlog_incfile vhdl_file.vhd vhdl_lfile vhdl2008_file xci_file.xci xdc_file.xdc bootrom.mem another_sv_file.sv | pre_build
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$(EDALIZE_LAUNCHER) vivado -notrace -mode batch -source design.tcl
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design.v design.edn: design_synth.tcl design_netlist.tcl design.xpr.marker | pre_build design.xpr
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$(EDALIZE_LAUNCHER) vivado -notrace -mode batch -source design_synth.tcl design_netlist.tcl design.xpr
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synth: design.v design.edn | pre_build
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design.bit: design_synth.tcl design_run.tcl design.xpr.marker | pre_build design.xpr
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$(EDALIZE_LAUNCHER) vivado -notrace -mode batch -source design_synth.tcl design_run.tcl design.xpr
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build-gui: design.xpr | pre_build
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$(EDALIZE_LAUNCHER) vivado design.xpr
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pgm: design_pgm.tcl design.bit | pre_build
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$(EDALIZE_LAUNCHER) vivado -quiet -nolog -notrace -mode batch -source design_pgm.tcl -tclargs xc7a35tcsg324-1 design.bit
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post_build: design.bit
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pre_run:
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run: pre_run
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post_run: run

‎tests/flows/vivado/design.tcl‎

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# Auto-generated project tcl file
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create_project design -force
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set_property part xc7a35tcsg324-1 [current_project]
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#Default since Vivado 2016.1
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set_param project.enableVHDL2008 1
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set_property generic {vlogparam_bool=1 vlogparam_int=42 vlogparam_str=hello } [get_filesets sources_1]
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set_property verilog_define {vlogdefine_bool=1 vlogdefine_int=42 vlogdefine_str=hello } [get_filesets sources_1]
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read_xdc -unmanaged {sdc_file}
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read_verilog -sv {sv_file.sv}
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source {tcl_file.tcl}
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read_verilog {vlog_file.v}
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read_verilog {vlog_with_define.v}
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read_verilog {vlog05_file.v}
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read_vhdl {vhdl_file.vhd}
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read_vhdl -library libx {vhdl_lfile}
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read_vhdl -vhdl2008 {vhdl2008_file}
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read_ip {xci_file.xci}
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read_xdc {xdc_file.xdc}
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read_mem {bootrom.mem}
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read_verilog -sv {another_sv_file.sv}
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set_property include_dirs [list . .] [get_filesets sources_1]
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set_property top top_module [current_fileset]
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set_property source_mgmt_mode None [current_project]
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# Vivado treats IP integrator entities as nested sub-designs and prevents core
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# generation from the base project in non-GUI flow raising
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# ERROR: [Vivado 12-3563] The Nested sub-design '...xci' can only be generated
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# by its parent sub-design.
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# These cores are created and generated separately by Tcl scripts.
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# exported from IP integrator. To prevent this error, Ip cores that are part of
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# a block design must be excluded from generation at the top level. This can be
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# done using `get_ips -filter {SCOPE !~ "*.bd"}`. In Vivado >= 2019.1 the same
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# can be achieved using `get_ips -exclude_bd_ips`
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upgrade_ip [get_ips -filter {SCOPE !~ "*.bd"}]
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generate_target all [get_ips -filter {SCOPE !~ "*.bd"}]
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# Update marker file for Make. (Run the subsequent jobs only if the marker has been updated)
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# This prevents the synthesis from being triggered again if Vivado randomly updates the XPR file's timestamp.
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set marker_file [open "design.xpr.marker" w]
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puts $marker_file [clock seconds]
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close $marker_file

‎tests/flows/vivado/design_netlist.tcl‎

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open_run synth_1
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write_edif [current_project].edn
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write_verilog [current_project].v

‎tests/flows/vivado/design_pgm.tcl‎

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# Auto-generated program tcl file
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set part [lindex $argv 0]
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set bitstream [lindex $argv 1]
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if {[info exists env(HW_TARGET)]} {
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set explicit_hw_target $env(HW_TARGET)
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} else {
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set explicit_hw_target ""
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}
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if {[info exists env(JTAG_FREQ)]} {
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set jtag_freq $env(JTAG_FREQ)
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} else {
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set jtag_freq ""
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}
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puts "FuseSoC Xilinx FPGA Programming Tool"
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puts "===================================="
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puts ""
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puts "INFO: Programming part $part with bitstream $bitstream"
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if { $explicit_hw_target != "" } {
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puts "INFO: Programming target $explicit_hw_target"
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}
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# Connect to Xilinx Hardware Server
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if { [ catch { open_hw_manager } ] } { open_hw }
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connect_hw_server
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if { $explicit_hw_target == "" } {
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set hw_targets [get_hw_targets]
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} else {
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set hw_targets [get_hw_targets $explicit_hw_target]
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}
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if { [llength $hw_targets] == 0 } {
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if { $explicit_hw_target == "" } {
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puts "ERROR: Failed to find any targets"
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} else {
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puts "ERROR: Failed to find target: $target"
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}
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}
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# Find the first target and device that contains a FPGA $part.
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set hw_device_found 0
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foreach hw_target $hw_targets {
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puts "INFO: Trying to use hardware target $hw_target"
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current_hw_target $hw_target
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# Open hardware target
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# The Vivado hardware server isn't always able to reliably open a target.
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# Try three times before giving up.
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set hw_target_opened 0
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for {set open_hw_target_try 1} {$open_hw_target_try <= 3} {incr open_hw_target_try} {
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if {[catch {open_hw_target} res_open_hw_target] == 0} {
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set hw_target_opened 1
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break
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}
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}
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if { $hw_target_opened == 0 } {
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puts "WARNING: Unable to open hardware target $hw_target after " \
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"$open_hw_target_try tries. Skipping."
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continue
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}
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puts "INFO: Opened hardware target $hw_target on try $open_hw_target_try."
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# Iterate through all devices and find one which contains $part
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foreach { hw_device } [get_hw_devices] {
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if { [string first [get_property PART $hw_device] $part] == 0 } {
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puts "INFO: Found $part as part of $hw_device."
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current_hw_device $hw_device
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set hw_device_found 1
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break
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}
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}
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if { $hw_device_found == 1 } {
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break
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} else {
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# Close currently tried device, and try with next one.
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puts "INFO: Part not found as part of $hw_target. Trying next device."
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close_hw_target
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}
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}
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if { $hw_device_found == 0 } {
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puts "ERROR: None of the hardware targets included a $part FPGA part. \
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Check cables and ensure that jumpers are correct for JTAG programming."
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exit 1
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}
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puts "INFO: Programming bitstream to device $hw_device on target $hw_target."
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# Do the programming
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current_hw_device $hw_device
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set_property PROGRAM.FILE $bitstream [current_hw_device]
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if {$jtag_freq != ""} {
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set_property PARAM.FREQUENCY $jtag_freq [get_hw_targets $hw_target]
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}
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program_hw_devices [current_hw_device]
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# Disconnect from Xilinx Hardware Server
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close_hw_target
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disconnect_hw_server
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puts ""
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puts "INFO: SUCCESS! FPGA $part successfully programmed with bitstream $bitstream."

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