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FPGA: modify matrix multiply sample to use variable latency MM hosts
Updates the three DMA kernels to use variable rather than fixed latency MM hosts when compiling in the IP authoring flow.
2 parents c7c6dd6 + 4840e06 commit d520f10

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DirectProgramming/C++SYCL_FPGA/ReferenceDesigns/matmul/src/memory_transfers.hpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -39,7 +39,7 @@ class MatrixReadFromDDRToPipeA {
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mmhost(aspace, // buffer_location or aspace
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28, // address width
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dwidth, // data width
42-
16, // latency
42+
0, // latency
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1, // read_write_mode, 0: ReadWrite, 1: Read, 2: Write
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1, // maxburst
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0, // align, 0 defaults to alignment of the type
@@ -192,7 +192,7 @@ class MatrixReadFromDDRToPipeB {
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mmhost(aspace, // buffer_location or aspace
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28, // address width
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dwidth, // data width
195-
16, // latency
195+
0, // latency
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1, // read_write_mode, 0: ReadWrite, 1: Read, 2: Write
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1, // maxburst
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0, // align, 0 defaults to alignment of the type
@@ -337,7 +337,7 @@ class MatrixReadPipeToDDR {
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mmhost(aspace, // buffer_location or aspace
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28, // address width
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dwidth, // data width
340-
16, // latency
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0, // latency
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2, // read_write_mode, 0: ReadWrite, 1: Read, 2: Write
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1, // maxburst
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0, // align, 0 defaults to alignment of the type

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