MUXI2 Verilog functional models resolve to X for all known input combinations

[WilliamHHL]

Context

I was running a post-layout gate-level simulation of a CPU synthesized with the
ICS55 standard-cell libraries. The simulation failed because X values
appeared shortly after reset was released.

I tested netlists from several implementation stages, including post-synthesis,
post-fanout-fix, routed, and STA output. The problem was already present in the
post-synthesis simulation, so it was not introduced by routing, parasitic
extraction, or SDF annotation.

I initially suspected an RTL reset or uninitialized-state problem. However:

• The four-state RTL simulation passes.
• The relevant sequential state becomes known after the active reset clock
  edge and remains known while reset is asserted.
• The same RTL synthesized with SKY130 standard cells passes four-state
  post-synthesis simulation using the unmodified SKY130 functional models.
• Correcting only the ICS55 MUXI2 functional model allows the unchanged
  ICS55 synthesis and routed netlists to pass the same CPU/SoC test.

The failure was reduced to a standalone standard-cell test.

Affected files

IP/STD_cell/ics55_LLSC_H7C_V1p10C100/ics55_LLSC_H7CL/verilog/ics55_LLSC_H7CL.v
IP/STD_cell/ics55_LLSC_H7C_V1p10C100/ics55_LLSC_H7CR/verilog/ics55_LLSC_H7CR.v
IP/STD_cell/ics55_LLSC_H7C_V1p10C100/ics55_LLSC_H7CH/verilog/ics55_LLSC_H7CH.v

All seven MUXI2 drive-strength variants in each of H7L, H7R, and H7H appear
to contain the same pattern, for a total of 21 affected modules.

For example:

MUXI2X0P5H7R
MUXI2X0P7H7R
MUXI2X1H7R
MUXI2X1P4H7R
MUXI2X2H7R
MUXI2X3H7R
MUXI2X4H7R

Problematic model

For example, MUXI2X0P5H7R contains:

module MUXI2X0P5H7R (Y, A, B, S0);
output Y;
input A, B, S0;

  udp_mux2 u0(Y, A, B, S0);
  not      u1(Y, Y);

endmodule

Y is driven by both the mux UDP and the inverter, and the inverter uses Y
as both its input and output. This creates multiple drivers and a combinational
self-feedback path.

The supplied udp_mux2 is a non-inverting mux. The corresponding Liberty
function is:

function : "(!A * !S0) + (!B * S0)";

This is equivalent to:

Y = ~(S0 ? B : A);

Minimal reproducer

`timescale 1ns/1ps

module muxi2_model_tb;
    reg a;
    reg b;
    reg s;
    reg expected;
    wire y;
    integer vector;
    integer errors;

    MUXI2X0P5H7R dut (
        .A  (a),
        .B  (b),
        .S0 (s),
        .Y  (y)
    );

    initial begin
        errors = 0;

        for (vector = 0; vector < 8; vector = vector + 1) begin
            {s, b, a} = vector[2:0];
            expected = ~(s ? b : a);
            #1;

            $display(
                "A=%b B=%b S0=%b Y=%b EXPECTED=%b",
                a, b, s, y, expected
            );

            if (y !== expected)
                errors = errors + 1;
        end

        if (errors == 0)
            $display("MUXI2_MODEL_PASS");
        else
            $display("MUXI2_MODEL_FAIL errors=%0d", errors);

        $finish;
    end
endmodule

Run with:

iverilog -g2012 -Dfunctional \
  -s muxi2_model_tb \
  -o muxi2_original \
  IP/STD_cell/ics55_LLSC_H7C_V1p10C100/ics55_LLSC_H7CR/verilog/ics55_LLSC_H7CR.v \
  muxi2_model_tb.v

vvp muxi2_original

Tested with Icarus Verilog 12.0.

Actual result

Every known input combination produces X:

A=0 B=0 S0=0 Y=x EXPECTED=1
A=1 B=0 S0=0 Y=x EXPECTED=0
A=0 B=1 S0=0 Y=x EXPECTED=1
A=1 B=1 S0=0 Y=x EXPECTED=0
A=0 B=0 S0=1 Y=x EXPECTED=1
A=1 B=0 S0=1 Y=x EXPECTED=1
A=0 B=1 S0=1 Y=x EXPECTED=0
A=1 B=1 S0=1 Y=x EXPECTED=0
MUXI2_MODEL_FAIL errors=8

Expected result

All eight vectors should match the Liberty truth table and produce:

MUXI2_MODEL_PASS

Proposed correction

An intermediate net removes the multiple-driver/self-feedback problem:

module MUXI2X0P5H7R (Y, A, B, S0);
output Y;
input A, B, S0;

  wire muxi2_y;

  udp_mux2 u0(muxi2_y, A, B, S0);
  not      u1(Y, muxi2_y);

endmodule

With this correction, all eight standalone truth-table vectors pass. The
unchanged CPU synthesis and routed netlists also pass the same gate-level
functional test.

SKY130 comparison

As a control experiment, the same CPU RTL was synthesized to
sky130_fd_sc_hd and simulated using the unmodified SKY130 functional models.
The post-synthesis four-state simulation completed successfully with no
unknown values on the active memory interface.

The equivalent SKY130 inverted mux model uses an intermediate signal between
the mux UDP and output buffer, avoiding multiple drivers.

Scope of this report

This issue reports a defect in the delivered Verilog functional simulation
model. It does not claim that the physical standard cell, GDS, or Liberty
timing data is defective. The Liberty logical function agrees with the
proposed corrected model.

Could you please confirm the intended implementation and update the affected
H7L, H7R, and H7H MUXI2 Verilog models?