Fix typos (#3041)

Co-authored-by: Joseph Baker <joseph.baker@codethink.co.uk>

Author: nazar-codethink

core/amo_buffer.sv

@@ -11,7 +11,7 @@
 // Author: Florian Zaruba, ETH Zurich
 // Date: 20.09.2018
 // Description: Buffers AMO requests
-// This unit buffers an atomic memory operations for the cache subsystem.
+// This unit buffers an atomic memory operation for the cache subsystem.
 // Furthermore it handles interfacing with the commit stage
 
 module amo_buffer #(

core/cache_subsystem/wt_cache_subsystem.sv

@@ -91,7 +91,7 @@ module wt_cache_subsystem
     logic [CVA6Cfg.XLEN-1:0] data;  // word width of processor (no block stores at the moment)
     logic [CVA6Cfg.DCACHE_USER_WIDTH-1:0]          user;        // user width of processor (no block stores at the moment)
     logic nc;  // noncacheable
-    logic [CVA6Cfg.MEM_TID_WIDTH-1:0] tid;  // threadi id (used as transaction id in Ariane)
+    logic [CVA6Cfg.MEM_TID_WIDTH-1:0] tid;  // thread id (used as transaction id in Ariane)
     ariane_pkg::amo_t amo_op;  // amo opcode
   };
 
@@ -100,7 +100,7 @@ module wt_cache_subsystem
     logic [CVA6Cfg.DCACHE_LINE_WIDTH-1:0] data;  // full cache line width
     logic [CVA6Cfg.DCACHE_USER_LINE_WIDTH-1:0] user;  // user bits
     dcache_inval_t inv;  // invalidation vector
-    logic [CVA6Cfg.MEM_TID_WIDTH-1:0] tid;  // threadi id (used as transaction id in Ariane)
+    logic [CVA6Cfg.MEM_TID_WIDTH-1:0] tid;  // thread id (used as transaction id in Ariane)
   };
 
   logic icache_adapter_data_req, adapter_icache_data_ack, adapter_icache_rtrn_vld;

core/cache_subsystem/wt_dcache_missunit.sv

@@ -53,7 +53,7 @@ module wt_dcache_missunit
     output logic [NumPorts-1:0] miss_replay_o,
     // signals response from memory
     output logic [NumPorts-1:0] miss_rtrn_vld_o,
-    output logic [CVA6Cfg.MEM_TID_WIDTH-1:0]                  miss_rtrn_id_o,     // only used for writes, set to zero fro reads
+    output logic [CVA6Cfg.MEM_TID_WIDTH-1:0]                  miss_rtrn_id_o,     // only used for writes, set to zero for reads
     // from writebuffer
     input  logic [CVA6Cfg.DCACHE_MAX_TX-1:0][CVA6Cfg.PLEN-1:0]  tx_paddr_i,         // used to check for address collisions with read operations
     input  logic [CVA6Cfg.DCACHE_MAX_TX-1:0]                   tx_vld_i,           // used to check for address collisions with read operations

core/commit_stage.sv

@@ -72,7 +72,7 @@ module commit_stage
     output logic [CVA6Cfg.TRANS_ID_BITS-1:0] commit_tran_id_o,
     // Valid AMO in commit stage - EX_STAGE
     output logic amo_valid_commit_o,
-    // no store is pending - EX_STAGE
+    // No store is pending - EX_STAGE
     input logic no_st_pending_i,
     // Commit the pending CSR instruction - EX_STAGE
     output logic commit_csr_o,

core/cva6.sv

@@ -191,7 +191,7 @@ module cva6
         logic [CVA6Cfg.ICACHE_INDEX_WIDTH-1:0]     idx;  // physical address to invalidate
         logic [CVA6Cfg.ICACHE_SET_ASSOC_WIDTH-1:0] way;  // way to invalidate
       } inv;  // invalidation vector
-      logic [CVA6Cfg.MEM_TID_WIDTH-1:0] tid;  // threadi id (used as transaction id in Ariane)
+      logic [CVA6Cfg.MEM_TID_WIDTH-1:0] tid;  // thread id (used as transaction id in Ariane)
     },
 
     // D$ data requests

core/ex_stage.sv

@@ -214,7 +214,7 @@ module ex_stage
     input icache_arsp_t icache_areq_i,
     // icache translation request - CACHE
     output icache_areq_t icache_areq_o,
-    // Data cache request ouput - CACHE
+    // Data cache request output - CACHE
     input dcache_req_o_t [2:0] dcache_req_ports_i,
     // Data cache request input - CACHE
     output dcache_req_i_t [2:0] dcache_req_ports_o,

core/frontend/instr_queue.sv

@@ -76,7 +76,7 @@ module instr_queue
     input logic [CVA6Cfg.VLEN-1:0] predict_address_i,
     // Instruction predict address - FRONTEND
     input ariane_pkg::cf_t [CVA6Cfg.INSTR_PER_FETCH-1:0] cf_type_i,
-    // Replay instruction because one of the FIFO was  full - FRONTEND
+    // Replay instruction because one of the FIFO was full - FRONTEND
     output logic replay_o,
     // Address at which to replay the fetch - FRONTEND
     output logic [CVA6Cfg.VLEN-1:0] replay_addr_o,

core/id_stage.sv

@@ -91,7 +91,7 @@ module id_stage #(
     input x_compressed_resp_t compressed_resp_i,
     output logic compressed_valid_o,
     output x_compressed_req_t compressed_req_o,
-    // Data cache request ouput - CACHE
+    // Data cache request output - CACHE
     input dcache_req_o_t dcache_req_ports_i,
     // Data cache request input - CACHE
     output dcache_req_i_t dcache_req_ports_o

core/include/wt_cache_pkg.sv

@@ -22,7 +22,7 @@
 
 package wt_cache_pkg;
 
-  // these parames need to coincide with the
+  // these parameters need to coincide with the
   // L1.5 parameterization, do not change
 `ifdef PITON_ARIANE
 

core/issue_read_operands.sv

@@ -746,7 +746,7 @@ module issue_read_operands
     end
   end
   // FU select, assert the correct valid out signal (in the next cycle)
-  // This needs to be like this to make verilator happy. I know its ugly.
+  // This needs to be like this to make verilator happy. I know it's ugly.
   always_ff @(posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
       alu_valid_q    <= '0;