verible

AngelaGonzalezMarino · AngelaGonzalezMarino · commit 29ab194788e0 · 2026-07-07T13:11:16.000+02:00
diff --git a/core/cva6_mmu/cva6_mmu.sv b/core/cva6_mmu/cva6_mmu.sv
@@ -168,7 +168,7 @@ module cva6_mmu
   logic shared_tlb_hit, itlb_req;
   logic aborted_ptw_req;
 
-   exception_t misaligned_ex_q;
+  exception_t misaligned_ex_q;
 
   // Assignments
 
