Resolving addressed lines

Author: ahmadtkhan

core/cva6_mmu/cva6_mmu.sv

@@ -103,6 +103,7 @@ module cva6_mmu
     output dcache_req_i_t req_port_o,
 
     // PMP
+
     input riscv::pmpcfg_t [avoid_neg(CVA6Cfg.NrPMPEntries-1):0]                   pmpcfg_i,
     input logic           [avoid_neg(CVA6Cfg.NrPMPEntries-1):0][CVA6Cfg.PLEN-3:0] pmpaddr_i
 );
@@ -172,8 +173,6 @@ module cva6_mmu
 
   logic shared_tlb_access, shared_tlb_miss;
   logic shared_tlb_hit, itlb_req;
-  //logic shared_tlb_lookup_done;
-
   // Assignments
 
   assign itlb_lu_access = icache_areq_i.fetch_req;

core/cva6_mmu/cva6_shared_tlb.sv

@@ -18,7 +18,8 @@
 //              shared TLB sv32 developed by Sebastien Jacq (Thales Research & Technology)
 //              to be used with sv32, sv39 and sv39x4.
 
-/* verilator lint_off WIDTH*/
+/* verilator lint_off WIDTH */
+
 module cva6_shared_tlb #(
     parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
     parameter type pte_cva6_t = logic,
@@ -97,6 +98,7 @@ module cva6_shared_tlb #(
     logic [HYP_EXT*2:0] v_st_enbl;  // v_i,g-stage enabled, s-stage enabled
     logic is_napot_64k;  // Svnapot: Flag indicating a 64KiB NAPOT page
   } shared_tag_t;
+
   shared_tag_t shared_tag_wr;
   shared_tag_t [SHARED_TLB_WAYS-1:0] shared_tag_rd;
 
@@ -468,6 +470,7 @@ module cva6_shared_tlb #(
   // ------------------
   // Update and Flush
   // ------------------
+
   logic [CVA6Cfg.VpnLen-1:0] vpn_to_store;
   logic [$clog2(CVA6Cfg.SharedTlbDepth)-1:0] vpn_index;
   //flushing signals
@@ -833,3 +836,5 @@ module cva6_shared_tlb #(
     end
   end
 endmodule
+
+/* verilator lint_on WIDTH */