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JeanRochCoulonJeanRochCoulon
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Merge branch 'master' into fix/amo_l15_adapter
2 parents a8c3859 + b30e7db commit 52083f4

29 files changed

Lines changed: 522 additions & 295 deletions

‎.github/workflows/verible.yml‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -22,3 +22,8 @@ jobs:
2222
github_token: ${{ secrets.GITHUB_TOKEN }}
2323
files: '$(find core -regex ".*\.\(v\|sv\)$" | grep -v "^core/include/.*_config_pkg\.sv$")'
2424
fail_on_formatting_suggestions: true
25+
- name: CVA6Cfg's XLEN attribute usage verificatory script
26+
if: always()
27+
run: |
28+
chmod +x util/sanitize/systemverilog/xlen_misuse.sh
29+
util/sanitize/systemverilog/xlen_misuse.sh

‎.gitlab-ci/expected_synth.yml‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,2 +1,2 @@
11
cv32a65x:
2-
gates: 183727
2+
gates: 182900

‎Bender.yml‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@ dependencies:
1010
axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.31.0 }
1111
common_cells:
1212
{ git: "https://github.com/pulp-platform/common_cells", version: 1.23.0 }
13-
fpnew: { git: "https://github.com/openhwgroup/cvfpu.git", rev: a74d99a32b } # branch: develop
13+
fpnew: { git: "https://github.com/openhwgroup/cvfpu.git", rev: 106251e } # branch: develop
1414
tech_cells_generic:
1515
{ git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.13 }
1616

‎core/acc_dispatcher.sv‎

Lines changed: 9 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -189,8 +189,6 @@ module acc_dispatcher
189189

190190
// We received a new instruction
191191
if (acc_valid_q) insn_pending_d[acc_data.trans_id] = 1'b1;
192-
// Flush all received instructions
193-
if (flush_ex_i) insn_pending_d = '0;
194192

195193
// An accelerator instruction is no longer speculative.
196194
if (acc_commit && insn_pending_q[acc_commit_trans_id]) begin
@@ -200,6 +198,15 @@ module acc_dispatcher
200198

201199
// An accelerator instruction was issued.
202200
if (acc_req_o.acc_req.req_valid) insn_ready_d[acc_req_o.acc_req.trans_id] = 1'b0;
201+
202+
// Flush all received instructions. This branch must appear LAST so that
203+
// it wins the lexical-priority contest against a simultaneous acc_commit
204+
// (which reads the registered insn_pending_q and would otherwise leave a
205+
// stale insn_ready bit set for a just-flushed trans_id).
206+
if (flush_ex_i) begin
207+
insn_pending_d = '0;
208+
insn_ready_d = '0;
209+
end
203210
end : p_non_speculative_ff
204211

205212
/*************************

‎core/alu.sv‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -319,7 +319,7 @@ module alu
319319
// Adder Operations
320320
ADD, SUB, ADDUW, SH1ADD, SH2ADD, SH3ADD: result_o = adder_result;
321321
// Shift Operations
322-
SLL, SRL, SRA: result_o = (CVA6Cfg.IS_XLEN64) ? shift_result : shift_result32;
322+
SLL, SRL, SRA: result_o = CVA6Cfg.IS_XLEN64 ? shift_result : shift_result32;
323323
// Comparison Operations
324324
SLTS, SLTU: result_o = {{CVA6Cfg.XLEN - 1{1'b0}}, less};
325325
default: ; // default case to suppress unique warning
@@ -368,10 +368,10 @@ module alu
368368

369369
// Bitwise Rotation
370370
ROL:
371-
result_o = (CVA6Cfg.IS_XLEN64) ? ((operand_a << operand_b[5:0]) | (operand_a >> (CVA6Cfg.XLEN-operand_b[5:0]))) : ((operand_a << operand_b[4:0]) | (operand_a >> (CVA6Cfg.XLEN-operand_b[4:0])));
371+
result_o = CVA6Cfg.IS_XLEN64 ? ((operand_a << operand_b[5:0]) | (operand_a >> (CVA6Cfg.XLEN-operand_b[5:0]))) : ((operand_a << operand_b[4:0]) | (operand_a >> (CVA6Cfg.XLEN-operand_b[4:0])));
372372

373373
ROR, RORI:
374-
result_o = (CVA6Cfg.IS_XLEN64) ? ((operand_a >> operand_b[5:0]) | (operand_a << (CVA6Cfg.XLEN-operand_b[5:0]))) : ((operand_a >> operand_b[4:0]) | (operand_a << (CVA6Cfg.XLEN-operand_b[4:0])));
374+
result_o = CVA6Cfg.IS_XLEN64 ? ((operand_a >> operand_b[5:0]) | (operand_a << (CVA6Cfg.XLEN-operand_b[5:0]))) : ((operand_a >> operand_b[4:0]) | (operand_a << (CVA6Cfg.XLEN-operand_b[4:0])));
375375

376376
ORCB: result_o = orcbw_result;
377377
REV8: result_o = rev8w_result;
@@ -394,9 +394,9 @@ module alu
394394
if (CVA6Cfg.ZKN && CVA6Cfg.RVB) begin
395395
unique case (fu_data_i.operation)
396396
PACK:
397-
result_o = (CVA6Cfg.IS_XLEN32) ? ({operand_b[15:0], operand_a[15:0]}) : ({operand_b[31:0], operand_a[31:0]});
397+
result_o = CVA6Cfg.IS_XLEN32 ? ({operand_b[15:0], operand_a[15:0]}) : ({operand_b[31:0], operand_a[31:0]});
398398
PACK_H:
399-
result_o = (CVA6Cfg.IS_XLEN32) ? ({16'b0, operand_b[7:0], operand_a[7:0]}) : ({48'b0, operand_b[7:0], operand_a[7:0]});
399+
result_o = CVA6Cfg.IS_XLEN32 ? ({16'b0, operand_b[7:0], operand_a[7:0]}) : ({48'b0, operand_b[7:0], operand_a[7:0]});
400400
BREV8: result_o = brev8_reversed;
401401
XPERM8: result_o = xperm8_result;
402402
XPERM4: result_o = xperm4_result;

‎core/cache_subsystem/cva6_hpdcache_if_adapter.sv‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -239,7 +239,7 @@ module cva6_hpdcache_if_adapter
239239

240240
assign amo_is_word = (cva6_amo_req_i.size == 2'b10);
241241
assign amo_is_word_hi = cva6_amo_req_i.operand_a[2];
242-
if (CVA6Cfg.XLEN == 64) begin : amo_data_64_gen
242+
if (CVA6Cfg.IS_XLEN64) begin : amo_data_64_gen
243243
assign amo_data = amo_is_word ? {2{cva6_amo_req_i.operand_b[0+:32]}} : cva6_amo_req_i.operand_b;
244244
assign amo_data_be = amo_is_word_hi ? 8'hf0 : amo_is_word ? 8'h0f : 8'hff;
245245
end else begin : amo_data_32_gen
@@ -327,8 +327,7 @@ module cva6_hpdcache_if_adapter
327327
// Response forwarding
328328
// {{{
329329
ariane_pkg::amo_resp_t cva6_amo_resp;
330-
331-
if (CVA6Cfg.XLEN == 64) begin : amo_resp_64_gen
330+
if (CVA6Cfg.IS_XLEN64) begin : amo_resp_64_gen
332331
assign amo_resp_word = amo_is_word_hi
333332
? hpdcache_rsp_i.rdata[0][32 +: 32]
334333
: hpdcache_rsp_i.rdata[0][0 +: 32];

‎core/csr_regfile.sv‎

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -334,7 +334,7 @@ module csr_regfile
334334
| (CVA6Cfg.XLEN'(CVA6Cfg.RVU) << 20) // U - User mode implemented
335335
| (CVA6Cfg.XLEN'(CVA6Cfg.RVV) << 21) // V - Vector extension
336336
| (CVA6Cfg.XLEN'(CVA6Cfg.NSX) << 23) // X - Non-standard extensions present
337-
| ((CVA6Cfg.XLEN == 64 ? 2 : 1) << CVA6Cfg.XLEN - 2); // MXL
337+
| ((CVA6Cfg.IS_XLEN64 ? 2 : 1) << CVA6Cfg.XLEN - 2); // MXL
338338

339339
assign pmpcfg_o = pmpcfg_q[(CVA6Cfg.NrPMPEntries>0?CVA6Cfg.NrPMPEntries-1 : 0):0];
340340
assign pmpaddr_o = pmpaddr_q[(CVA6Cfg.NrPMPEntries>0?CVA6Cfg.NrPMPEntries-1 : 0):0];
@@ -600,7 +600,7 @@ module csr_regfile
600600
// machine mode registers
601601
riscv::CSR_MSTATUS: csr_rdata = mstatus_extended;
602602
riscv::CSR_MSTATUSH:
603-
if (CVA6Cfg.XLEN == 32) csr_rdata = mstatush;
603+
if (CVA6Cfg.IS_XLEN32) csr_rdata = mstatush;
604604
else read_access_exception = 1'b1;
605605
riscv::CSR_MISA: csr_rdata = IsaCode;
606606
riscv::CSR_MEDELEG:
@@ -641,7 +641,7 @@ module csr_regfile
641641
end
642642
end
643643
riscv::CSR_MENVCFGH: begin
644-
if (CVA6Cfg.RVU && CVA6Cfg.XLEN == 32) csr_rdata = '0;
644+
if (CVA6Cfg.RVU && CVA6Cfg.IS_XLEN32) csr_rdata = '0;
645645
else read_access_exception = 1'b1;
646646
end
647647
riscv::CSR_MVENDORID: csr_rdata = {{CVA6Cfg.XLEN - 32{1'b0}}, OPENHWGROUP_MVENDORID};
@@ -654,26 +654,26 @@ module csr_regfile
654654
// Counters and Timers
655655
riscv::CSR_MCYCLE: csr_rdata = cycle_q[CVA6Cfg.XLEN-1:0];
656656
riscv::CSR_MCYCLEH:
657-
if (CVA6Cfg.XLEN == 32) csr_rdata = cycle_q[63:32];
657+
if (CVA6Cfg.IS_XLEN32) csr_rdata = cycle_q[63:32];
658658
else read_access_exception = 1'b1;
659659
riscv::CSR_MINSTRET: csr_rdata = instret_q[CVA6Cfg.XLEN-1:0];
660660
riscv::CSR_MINSTRETH:
661-
if (CVA6Cfg.XLEN == 32) csr_rdata = instret_q[63:32];
661+
if (CVA6Cfg.IS_XLEN32) csr_rdata = instret_q[63:32];
662662
else read_access_exception = 1'b1;
663663
riscv::CSR_CYCLE:
664664
if (CVA6Cfg.RVZicntr) csr_rdata = cycle_q[CVA6Cfg.XLEN-1:0];
665665
else read_access_exception = 1'b1;
666666
riscv::CSR_CYCLEH:
667667
if (CVA6Cfg.RVZicntr)
668-
if (CVA6Cfg.XLEN == 32) csr_rdata = cycle_q[63:32];
668+
if (CVA6Cfg.IS_XLEN32) csr_rdata = cycle_q[63:32];
669669
else read_access_exception = 1'b1;
670670
else read_access_exception = 1'b1;
671671
riscv::CSR_INSTRET:
672672
if (CVA6Cfg.RVZicntr) csr_rdata = instret_q[CVA6Cfg.XLEN-1:0];
673673
else read_access_exception = 1'b1;
674674
riscv::CSR_INSTRETH:
675675
if (CVA6Cfg.RVZicntr)
676-
if (CVA6Cfg.XLEN == 32) csr_rdata = instret_q[63:32];
676+
if (CVA6Cfg.IS_XLEN32) csr_rdata = instret_q[63:32];
677677
else read_access_exception = 1'b1;
678678
else read_access_exception = 1'b1;
679679
//Event Selector
@@ -768,7 +768,7 @@ module csr_regfile
768768
riscv::CSR_MHPM_COUNTER_29H,
769769
riscv::CSR_MHPM_COUNTER_30H,
770770
riscv::CSR_MHPM_COUNTER_31H :
771-
if (CVA6Cfg.XLEN == 32) csr_rdata = perf_data_i;
771+
if (CVA6Cfg.IS_XLEN32) csr_rdata = perf_data_i;
772772
else read_access_exception = 1'b1;
773773

774774
// Performance counters (User Mode - R/O Shadows)
@@ -837,7 +837,7 @@ module csr_regfile
837837
riscv::CSR_HPM_COUNTER_30H,
838838
riscv::CSR_HPM_COUNTER_31H :
839839
if (CVA6Cfg.RVZihpm) begin
840-
if (CVA6Cfg.XLEN == 32) csr_rdata = perf_data_i;
840+
if (CVA6Cfg.IS_XLEN32) csr_rdata = perf_data_i;
841841
else read_access_exception = 1'b1;
842842
end else begin
843843
read_access_exception = 1'b1;
@@ -875,10 +875,10 @@ module csr_regfile
875875
automatic logic [3:0] index = csr_addr.address[11:0] - riscv::CSR_PMPCFG0;
876876

877877
// if index is not even and XLEN==64, raise exception
878-
if (CVA6Cfg.XLEN == 64 && index[0] == 1'b1) read_access_exception = 1'b1;
878+
if (CVA6Cfg.IS_XLEN64 && index[0] == 1'b1) read_access_exception = 1'b1;
879879
else begin
880880
// The following line has no effect. It's here just to prevent the synthesizer from crashing
881-
if (CVA6Cfg.XLEN == 64) index = (index >> 1) << 1;
881+
if (CVA6Cfg.IS_XLEN64) index = (index >> 1) << 1;
882882
csr_rdata = pmpcfg_q[index*4+:CVA6Cfg.XLEN/8];
883883
end
884884
end
@@ -1565,7 +1565,7 @@ module csr_regfile
15651565
flush_o = 1'b1;
15661566
end
15671567
riscv::CSR_MSTATUSH: begin
1568-
if (CVA6Cfg.XLEN == 32) begin
1568+
if (CVA6Cfg.IS_XLEN32) begin
15691569
mstatus_d.mbe = ((csr_wdata & riscv::MSTATUSH_MBE) != 0);
15701570
// Mirror MBE
15711571
mstatus_d.sbe = mstatus_d.mbe;
@@ -1707,7 +1707,7 @@ module csr_regfile
17071707
end
17081708
end
17091709
riscv::CSR_MENVCFGH: begin
1710-
if (!CVA6Cfg.RVU || CVA6Cfg.XLEN != 32) update_access_exception = 1'b1;
1710+
if (!CVA6Cfg.RVU || !CVA6Cfg.IS_XLEN32) update_access_exception = 1'b1;
17111711
end
17121712
riscv::CSR_MCOUNTINHIBIT:
17131713
if (CVA6Cfg.PerfCounterEn)
@@ -1716,11 +1716,11 @@ module csr_regfile
17161716
// performance counters
17171717
riscv::CSR_MCYCLE: cycle_d[CVA6Cfg.XLEN-1:0] = csr_wdata;
17181718
riscv::CSR_MCYCLEH:
1719-
if (CVA6Cfg.XLEN == 32) cycle_d[63:32] = csr_wdata;
1719+
if (CVA6Cfg.IS_XLEN32) cycle_d[63:32] = csr_wdata;
17201720
else update_access_exception = 1'b1;
17211721
riscv::CSR_MINSTRET: instret_d[CVA6Cfg.XLEN-1:0] = csr_wdata;
17221722
riscv::CSR_MINSTRETH:
1723-
if (CVA6Cfg.XLEN == 32) instret_d[63:32] = csr_wdata;
1723+
if (CVA6Cfg.IS_XLEN32) instret_d[63:32] = csr_wdata;
17241724
else update_access_exception = 1'b1;
17251725
//Event Selector
17261726
riscv::CSR_MHPM_EVENT_3,
@@ -1819,7 +1819,7 @@ module csr_regfile
18191819
riscv::CSR_MHPM_COUNTER_30H,
18201820
riscv::CSR_MHPM_COUNTER_31H : begin
18211821
perf_we_o = 1'b1;
1822-
if (CVA6Cfg.XLEN == 32) perf_data_o = csr_wdata;
1822+
if (CVA6Cfg.IS_XLEN32) perf_data_o = csr_wdata;
18231823
else update_access_exception = 1'b1;
18241824
end
18251825

@@ -1856,7 +1856,7 @@ module csr_regfile
18561856
automatic logic [11:0] index = csr_addr.address[11:0] - riscv::CSR_PMPCFG0;
18571857

18581858
// if index is not even and XLEN==64, raise exception
1859-
if (CVA6Cfg.XLEN == 64 && index[0] == 1'b1) update_access_exception = 1'b1;
1859+
if (CVA6Cfg.IS_XLEN64 && index[0] == 1'b1) update_access_exception = 1'b1;
18601860
else begin
18611861
for (int i = 0; i < CVA6Cfg.XLEN / 8; i++) begin
18621862
if (!pmpcfg_q[index*4+i].locked) pmpcfg_d[index*4+i] = csr_wdata[i*8+:8];

‎core/cva6.sv‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -689,8 +689,9 @@ module cva6
689689
.clk_i,
690690
.rst_ni,
691691
.boot_addr_i (boot_addr_i[CVA6Cfg.VLEN-1:0]),
692-
.flush_bp_i (1'b0),
693-
.flush_i (flush_ctrl_if), // not entirely correct
692+
.flush_bp_i ((CVA6Cfg.RVU || CVA6Cfg.RVS) ? flush_ctrl_bp : 1'b0),
693+
// below line is not entirely correct
694+
.flush_i (flush_ctrl_if),
694695
.halt_i (halt_ctrl),
695696
.halt_frontend_i (halt_frontend),
696697
.set_pc_commit_i (set_pc_ctrl_pcgen),

‎core/cva6_mmu/cva6_mmu.sv‎

Lines changed: 11 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -365,7 +365,7 @@ module cva6_mmu
365365
always_comb begin : instr_interface
366366
// MMU disabled: just pass through
367367
icache_areq_o.fetch_valid = icache_areq_i.fetch_req;
368-
icache_areq_o.fetch_paddr = CVA6Cfg.PLEN'(icache_areq_i.fetch_vaddr[((CVA6Cfg.PLEN > CVA6Cfg.VLEN) ? CVA6Cfg.VLEN -1: CVA6Cfg.PLEN -1 ):0]);
368+
icache_areq_o.fetch_paddr = CVA6Cfg.PLEN'(icache_areq_i.fetch_vaddr[((CVA6Cfg.PLEN > CVA6Cfg.VLEN) ? CVA6Cfg.VLEN -1: CVA6Cfg.PLEN -1 ):0]);
369369
// two potential exception sources:
370370
// 1. HPTW threw an exception -> signal with a page fault exception
371371
// 2. We got an access error because of insufficient permissions -> throw an access exception
@@ -382,9 +382,12 @@ module cva6_mmu
382382
// AXI decode error), or when PTW performs walk due to ITLB miss and raises
383383
// an error.
384384
if ((enable_translation_i || enable_g_translation_i)) begin
385-
// we work with SV39 or SV32, so if VM is enabled, check that all bits [CVA6Cfg.VLEN-1:CVA6Cfg.SV-1] are equal
386-
if (icache_areq_i.fetch_req && !((&icache_areq_i.fetch_vaddr[CVA6Cfg.VLEN-1:CVA6Cfg.SV-1]) == 1'b1 || (|icache_areq_i.fetch_vaddr[CVA6Cfg.VLEN-1:CVA6Cfg.SV-1]) == 1'b0)) begin
387-
385+
// If second-level address translation is enabled:
386+
// - in VS stage, check that all bits [CVA6Cfg.VLEN-1:CVA6Cfg.SV-1] are equal
387+
// - in pure G stage (SV39x4 mode), [CVA6Cfg.VLEN-1:CVA6Cfg.GPLEN] must be zero.
388+
// - in pure G stage (SV32x4 mode), no check is needed.
389+
if ((enable_translation_i && (icache_areq_i.fetch_req && !((&icache_areq_i.fetch_vaddr[CVA6Cfg.VLEN-1:CVA6Cfg.SV-1]) == 1'b1 || (|icache_areq_i.fetch_vaddr[CVA6Cfg.VLEN-1:CVA6Cfg.SV-1]) == 1'b0)))
390+
|| (enable_g_translation_i && !enable_translation_i && CVA6Cfg.IS_XLEN64 && (|icache_areq_i.fetch_vaddr[CVA6Cfg.VLEN-1:CVA6Cfg.GPLEN] != 1'b0))) begin
388391
icache_areq_o.fetch_exception.cause = riscv::INSTR_PAGE_FAULT;
389392
icache_areq_o.fetch_exception.valid = 1'b1;
390393
if (CVA6Cfg.TvalEn)
@@ -473,7 +476,7 @@ module cva6_mmu
473476
end else begin
474477
icache_areq_o.fetch_exception.cause = riscv::INSTR_ACCESS_FAULT;
475478
icache_areq_o.fetch_exception.valid = 1'b1;
476-
if (CVA6Cfg.TvalEn) //To confirm this is the right TVAL
479+
if (CVA6Cfg.TvalEn) // To confirm this is the right TVAL
477480
icache_areq_o.fetch_exception.tval = CVA6Cfg.XLEN'(update_vaddr);
478481
if (CVA6Cfg.RVH) begin
479482
icache_areq_o.fetch_exception.tval2 = '0;
@@ -535,7 +538,7 @@ module cva6_mmu
535538
if (CVA6Cfg.RVH) begin
536539
lsu_tinst_n = lsu_tinst_i;
537540
hs_ld_st_inst_n = hs_ld_st_inst_i;
538-
lsu_gpaddr_n[(CVA6Cfg.XLEN == 32 ? CVA6Cfg.VLEN: CVA6Cfg.GPLEN)-1:0] = dtlb_gpaddr[(CVA6Cfg.XLEN == 32 ? CVA6Cfg.VLEN: CVA6Cfg.GPLEN)-1:0];
541+
lsu_gpaddr_n[(CVA6Cfg.IS_XLEN32 ? CVA6Cfg.VLEN: CVA6Cfg.GPLEN)-1:0] = dtlb_gpaddr[(CVA6Cfg.IS_XLEN32 ? CVA6Cfg.VLEN: CVA6Cfg.GPLEN)-1:0];
539542
csr_hs_ld_st_inst_o = hs_ld_st_inst_i || hs_ld_st_inst_q;
540543
d_g_st_access_err = en_ld_st_g_translation_i && !dtlb_gpte_q.u;
541544
dtlb_gpte_n = dtlb_g_content;
@@ -590,7 +593,7 @@ module cva6_mmu
590593
{CVA6Cfg.XLEN - CVA6Cfg.VLEN{lsu_vaddr_q[CVA6Cfg.VLEN-1]}}, lsu_vaddr_q
591594
};
592595
if (CVA6Cfg.RVH) begin
593-
lsu_exception_o.tval2 = CVA6Cfg.GPLEN'(lsu_gpaddr_q[(CVA6Cfg.XLEN==32 ? CVA6Cfg.VLEN : CVA6Cfg.GPLEN)-1:0]);
596+
lsu_exception_o.tval2 = CVA6Cfg.GPLEN'(lsu_gpaddr_q[(CVA6Cfg.IS_XLEN32 ? CVA6Cfg.VLEN : CVA6Cfg.GPLEN)-1:0]);
594597
lsu_exception_o.tinst = '0;
595598
lsu_exception_o.gva = ld_st_v_i;
596599
end
@@ -617,7 +620,7 @@ module cva6_mmu
617620
{CVA6Cfg.XLEN - CVA6Cfg.VLEN{lsu_vaddr_q[CVA6Cfg.VLEN-1]}}, lsu_vaddr_q
618621
};
619622
if (CVA6Cfg.RVH) begin
620-
lsu_exception_o.tval2 = CVA6Cfg.GPLEN'(lsu_gpaddr_q[(CVA6Cfg.XLEN==32 ? CVA6Cfg.VLEN : CVA6Cfg.GPLEN)-1:0]);
623+
lsu_exception_o.tval2 = CVA6Cfg.GPLEN'(lsu_gpaddr_q[(CVA6Cfg.IS_XLEN32 ? CVA6Cfg.VLEN : CVA6Cfg.GPLEN)-1:0]);
621624
lsu_exception_o.tinst = '0;
622625
lsu_exception_o.gva = ld_st_v_i;
623626
end

‎core/cva6_mmu/cva6_ptw.sv‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -262,7 +262,7 @@ module cva6_ptw
262262
);
263263

264264

265-
assign req_port_o.data_be = CVA6Cfg.XLEN == 32 ? be_gen_32(
265+
assign req_port_o.data_be = CVA6Cfg.IS_XLEN32 ? be_gen_32(
266266
req_port_o.address_index[1:0], req_port_o.data_size
267267
) : '1;
268268

@@ -427,7 +427,7 @@ module cva6_ptw
427427
// Invalid PTE
428428
// -------------
429429
// If pte.v = 0, or if pte.r = 0 and pte.w = 1, or if pte.reserved !=0 in sv39 and sv39x4, stop and raise a page-fault exception.
430-
if (!pte.v || (!pte.r && pte.w) || (|pte.reserved && CVA6Cfg.XLEN == 64) || (!CVA6Cfg.SvnapotEn && pte.n) || (CVA6Cfg.SvnapotEn && !(pte.r || pte.x) && pte.n))
430+
if (!pte.v || (!pte.r && pte.w) || (|pte.reserved && CVA6Cfg.IS_XLEN64) || (!CVA6Cfg.SvnapotEn && pte.n) || (CVA6Cfg.SvnapotEn && !(pte.r || pte.x) && pte.n))
431431
state_d = PROPAGATE_ERROR;
432432
// -----------
433433
// Valid PTE

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