Fix linting (#3120)

- Tie off unassigned signals
- Fix partial signal assignments
- Add missing default in non-unique case statement

Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>

Author: ezelioli

core/cache_subsystem/cache_ctrl.sv

@@ -128,6 +128,7 @@ module cache_ctrl
     req_port_o.data_rvalid = 1'b0;
     req_port_o.data_rdata = '0;
     req_port_o.data_rid = mem_req_q.id;
+    req_port_o.data_ruser = '0;
     miss_req_o = '0;
     mshr_addr_o = '0;
     // Memory array communication

core/cva6.sv

@@ -820,6 +820,13 @@ module cva6
     assign wt_valid_ex_id[ACC_WB] = acc_valid_ex_id;
   end else begin
     assign cvxif_req = '0;
+    assign x_compressed_ready = '0;
+    assign x_compressed_resp = '0;
+    assign x_issue_ready = '0;
+    assign x_issue_resp = '0;
+    assign x_register_ready = '0;
+    assign x_result_valid = '0;
+    assign x_result = '0;
   end
 
   if (CVA6Cfg.CvxifEn && CVA6Cfg.EnableAccelerator) begin : gen_err_xif_and_acc
@@ -1477,7 +1484,8 @@ module cva6
         .noc_req_o (noc_req_o),
         .noc_resp_i(noc_resp_i)
     );
-    assign inval_ready = 1'b1;
+    assign inval_ready   = 1'b1;
+    assign miss_vld_bits = '0;
   end else begin : gen_cache_wb
     std_cache_subsystem #(
         // note: this only works with one cacheable region
@@ -1530,6 +1538,7 @@ module cva6
     );
     assign dcache_commit_wbuffer_not_ni = 1'b1;
     assign inval_ready                  = 1'b1;
+    assign miss_vld_bits                = '0;
   end
 
   // ----------------

core/cva6_mmu/cva6_ptw.sv

@@ -157,6 +157,8 @@ module cva6_ptw
   assign req_port_o.data_wdata = '0;
   // we only issue one single request at a time
   assign req_port_o.data_id = '0;
+  // user field not used
+  assign req_port_o.data_wuser = '0;
 
   // -----------
   // TLB Update
@@ -541,6 +543,7 @@ module cva6_ptw
                         pte.ppn, vaddr_lvl[HYP_EXT*2][ptw_lvl_q[0]], (CVA6Cfg.PtLevels)'(0)
                       };
                     end
+                    default: ;
                   endcase
                 end else ptw_pptr_n = {pte.ppn, vaddr_lvl[0][ptw_lvl_q[0]], (CVA6Cfg.PtLevels)'(0)};
 

core/cva6_mmu/cva6_shared_tlb.sv

@@ -201,10 +201,11 @@ module cva6_shared_tlb #(
   endgenerate
 
   if (CVA6Cfg.RVH)  //THIS UPDATES THE EXTRA BITS OF VPN IN SV39x4
-    assign vpn_d[CVA6Cfg.PtLevels][(CVA6Cfg.VpnLen%CVA6Cfg.PtLevels)-1:0] = ((|v_st_enbl[1][HYP_EXT:0]) && itlb_access_i && ~itlb_hit_i && ~dtlb_access_i) ? //
-        itlb_vaddr_i[CVA6Cfg.VpnLen-1:CVA6Cfg.VpnLen-(CVA6Cfg.VpnLen%CVA6Cfg.PtLevels)] :  //
+    assign vpn_d[CVA6Cfg.PtLevels] = ((|v_st_enbl[1][HYP_EXT:0]) && itlb_access_i && ~itlb_hit_i && ~dtlb_access_i) ? //
+        {{(((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)-(CVA6Cfg.VpnLen%CVA6Cfg.PtLevels))){1'b0}}, itlb_vaddr_i[CVA6Cfg.VpnLen-1:CVA6Cfg.VpnLen-(CVA6Cfg.VpnLen%CVA6Cfg.PtLevels)]} :  //
         (((|v_st_enbl[0][HYP_EXT:0]) && dtlb_access_i && ~dtlb_hit_i) ?  //
-        dtlb_vaddr_i[CVA6Cfg.VpnLen-1: CVA6Cfg.VpnLen-(CVA6Cfg.VpnLen%CVA6Cfg.PtLevels)] : vpn_q[CVA6Cfg.PtLevels][(CVA6Cfg.VpnLen%CVA6Cfg.PtLevels)-1:0]);
+        {{(((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)-(CVA6Cfg.VpnLen%CVA6Cfg.PtLevels))){1'b0}}, dtlb_vaddr_i[CVA6Cfg.VpnLen-1: CVA6Cfg.VpnLen-(CVA6Cfg.VpnLen%CVA6Cfg.PtLevels)]} : //
+        {{(((CVA6Cfg.VpnLen/CVA6Cfg.PtLevels)-(CVA6Cfg.VpnLen%CVA6Cfg.PtLevels))){1'b0}}, vpn_q[CVA6Cfg.PtLevels][(CVA6Cfg.VpnLen%CVA6Cfg.PtLevels)-1:0]});
 
   ///////////////////////////////////////////////////////
   // tag comparison, hit generation
@@ -411,7 +412,10 @@ module cva6_shared_tlb #(
     end
     if (CVA6Cfg.RVH) begin : gen_shared_tag_hyp
       //THIS UPDATES THE EXTRA BITS OF VPN IN SV39x4
-      assign shared_tag_wr.vpn[CVA6Cfg.PtLevels][(CVA6Cfg.VpnLen%CVA6Cfg.PtLevels)-1:0] = shared_tlb_update_i.vpn[CVA6Cfg.VpnLen-1: CVA6Cfg.VpnLen-(CVA6Cfg.VpnLen%CVA6Cfg.PtLevels)];
+      assign shared_tag_wr.vpn[CVA6Cfg.PtLevels] = {
+        {(((CVA6Cfg.VpnLen / CVA6Cfg.PtLevels) - (CVA6Cfg.VpnLen % CVA6Cfg.PtLevels))) {1'b0}},
+        shared_tlb_update_i.vpn[CVA6Cfg.VpnLen-1:CVA6Cfg.VpnLen-(CVA6Cfg.VpnLen%CVA6Cfg.PtLevels)]
+      };
     end
   endgenerate
 
@@ -503,6 +507,8 @@ module cva6_shared_tlb #(
         );
         assign pte[i][a] = pte_cva6_t'(pte_rd_data[i][a]);
       end
+    end else begin
+      assign shared_tag_rd[i] = '0;
     end
   end
 endmodule

core/ex_stage.sv

@@ -636,6 +636,8 @@ module ex_stage
     assign x_exception_o    = '0;
     assign x_result_o       = '0;
     assign x_valid_o        = '0;
+    assign x_we_o           = '0;
+    assign x_rd_o           = '0;
   end
 
   if (CVA6Cfg.RVS) begin

core/load_store_unit.sv

@@ -353,6 +353,7 @@ module load_store_unit
     assign dcache_req_ports_o[0].data_be       = '1;
     assign dcache_req_ports_o[0].data_size     = 2'b11;
     assign dcache_req_ports_o[0].data_we       = 1'b0;
+    assign dcache_req_ports_o[0].data_wuser    = '0;
     assign dcache_req_ports_o[0].kill_req      = '0;
     assign dcache_req_ports_o[0].tag_valid     = 1'b0;
 

core/load_unit.sv

@@ -209,6 +209,8 @@ module load_unit
                                               CVA6Cfg.DCACHE_INDEX_WIDTH];
   // request id = index of the load buffer's entry
   assign req_port_o.data_id = ldbuf_windex;
+  // user field not used
+  assign req_port_o.data_wuser = '0;
   // directly forward exception fields (valid bit is set below)
   assign ex_o.cause = ex_i.cause;
   assign ex_o.tval = ex_i.tval;

core/multiplier.sv

@@ -144,6 +144,9 @@ module multiplier
         clmulr_q <= clmulr_d;
       end
     end
+  end else begin
+    assign clmul_q  = '0;
+    assign clmulr_q = '0;
   end
   // -----------------------
   // Output pipeline register