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JeanRochCoulonJeanRochCoulon
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Merge branch 'master' into svnapot-feature
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‎util/toolchain-builder/README.md‎

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@@ -53,6 +53,13 @@ upstream toolchain (default: GCC 13.1.0) for bare-metal 32-bit and 64-bit applic
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# 3. Build and install the toolchain (requires write+create permissions for $INSTALL_DIR.)
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bash build-toolchain.sh $INSTALL_DIR
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Additionally, after getting the GCC toolchain, you can apply
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`gcc-cva6-tune.patch` to add support for the `-mtune=cva6` option in GCC.
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```bash
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cd util/toolchain-builder/src/gcc && git apply ../../gcc-cva6-tune.patch
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```
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## File and directory structure
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The base infrastructure for building compilation toolchains consists of two scripts

‎util/toolchain-builder/gcc-cva6-tune.patch‎

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diff --git a/gcc/config/riscv/cva6.md b/gcc/config/riscv/cva6.md
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new file mode 100644
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index 000000000..2dc397ee1
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--- /dev/null
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+++ b/gcc/config/riscv/cva6.md
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@@ -0,0 +1,98 @@
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+(define_automaton "cva6")
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+
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+;; CVA6 core
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+;; This has 4 functional unit groups:
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+;; - ALU + Branch unit + Mult/Div + CSR
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+;; - Load unit
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+;; - Store Unit
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+;; - FPU + ALU2 (for the superscalar configuration)
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+
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+;; Issue ports
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+(define_cpu_unit "cva6_issue0" "cva6")
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+(define_cpu_unit "cva6_issue1" "cva6") ;; if superscalar
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+
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+;; Fixed-latency (or so-called) functional units
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+(define_cpu_unit "cva6_alu0" "cva6") ;; Includes the result bus
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+(define_cpu_unit "cva6_branch" "cva6")
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+(define_cpu_unit "cva6_mul" "cva6")
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+(define_cpu_unit "cva6_div" "cva6")
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+;; FIXME add CSR unit? (define_cpu_unit "cva6_csr" "cva6")
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+
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+;; Accelerator/CV-X-IF functional unit
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+(define_cpu_unit "cva6_cvxif" "cva6")
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+
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+;; Load-Store Unit
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+(define_cpu_unit "cva6_load" "cva6")
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+(define_cpu_unit "cva6_store" "cva6")
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+
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+;; FPU and ALU2 units
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+(define_cpu_unit "cva6_fpu" "cva6")
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+(define_cpu_unit "cva6_alu2" "cva6") ;; if superscalar
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+
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+;; ISSUE can be either ISSUE0 or ISSUE1
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+(define_reservation "cva6_issue" "cva6_issue0|cva6_issue1")
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+
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+;; ALU can be either ALU0 or ALU2, and ALU2 is preferred (if available)
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+(define_reservation "cva6_alu" "cva6_alu2|cva6_alu0")
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+
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+;; Most (integer) instructions are dispatched to the ALUs
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+;; (All instructions need an issue port first)
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+(define_insn_reservation "cva6_int" 1
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+ (and (eq_attr "tune" "cva6")
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+ (eq_attr "type" "const,arith,logical,shift,slt,move,fmove,auipc,nop,bitmanip,rotate,condmove"))
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+ "cva6_issue, cva6_alu")
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+;; ALU-ALU forwarding is possible between integer instructions
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+;;(define_bypass 0 "cva6_int" "cva6_int")
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+;; Actually disabled as it decreases performance for now
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+
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+;; Branches/jumps/calls use the branch unit and the first ALU
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+(define_insn_reservation "cva6_branch" 1
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+ (and (eq_attr "tune" "cva6")
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+ (eq_attr "type" "branch,jump,call"))
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+ "cva6_issue, cva6_branch+cva6_alu0")
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+;; When a branch is used, then the store unit is locked
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+(absence_set "cva6_store" "cva6_branch")
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+
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+;; Multiplications use the multiplier, then the result bus of the ALU
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+(define_insn_reservation "cva6_mul" 2 ;; 2 cycles before the result is available
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+ (and (eq_attr "tune" "cva6")
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+ (eq_attr "type" "imul"))
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+ "cva6_issue, cva6_mul, cva6_alu0")
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+
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+;; Divisions make the divider busy for a long time
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+(define_insn_reservation "cva6_div" 42 ;; FIXME use a realistic duration instead of 42
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+ (and (eq_attr "tune" "cva6")
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+ (eq_attr "type" "idiv"))
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+ "cva6_issue, cva6_div*42") ;; FIXME use a realistic duration instead of 42
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+;; FIXME the duration of the division can be XLEN-dependent
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+;; Using the divider prevents from using alu0 and mul (and vice versa)
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+(exclusion_set "cva6_div" "cva6_alu0,cva6_mul")
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+
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+;; Unknown/custom and accelerator transfer instructions use CV-X-IF
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+(define_insn_reservation "cva6_cvxif" 1 ;; FIXME update duration
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+ (and (eq_attr "tune" "cva6")
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+ (eq_attr "type" "mfc,mtc,unknown,multi"))
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+ "cva6_issue, cva6_cvxif")
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+
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+;; Load instructions, (int or float) use the load unit
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+(define_insn_reservation "cva6_load" 2 ;; latency = 2 cycles...
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+ (and (eq_attr "tune" "cva6")
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+ (eq_attr "type" "load,fpload"))
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+ "cva6_issue, cva6_load") ;; ... pipelined: unit busy for 1 cycle only
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+
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+;; Store instructions, (int or float) use the store unit
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+(define_insn_reservation "cva6_store" 2 ;; latency = 2 cycles...
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+ (and (eq_attr "tune" "cva6")
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+ (eq_attr "type" "store,fpstore"))
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+ "cva6_issue, cva6_store") ;; ... pipelined: unit busy for 1 cycle only
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+;; Cannot use load and store units simultaneously
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+(exclusion_set "cva6_load" "cva6_store")
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+
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+;; Floating point processing use the FPU for a long time
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+(define_insn_reservation "cva6_fp" 42 ;; FIXME use a realistic value instead of 42
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+ (and (eq_attr "tune" "cva6")
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+ (eq_attr "type" "fadd,fmul,fmadd,fdiv,fcmp,fcvt,fsqrt"))
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+ "cva6_fpu*42") ;; FIXME use a realistic value instead of 42
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+;; FIXME the duration of the FP ops can be XLEN-dependent
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+;; Using the FPU prevents from using alu2 (and vice versa)
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+(exclusion_set "cva6_fpu" "cva6_alu2") ;; if superscalar
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+
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+;; FIXME define reservation for the following instructions:
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+;; sfb_alu atomic
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diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
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index 7d87ab7ce..b0993fd48 100644
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--- a/gcc/config/riscv/riscv-cores.def
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+++ b/gcc/config/riscv/riscv-cores.def
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@@ -37,6 +37,7 @@ RISCV_TUNE("rocket", generic, rocket_tune_info)
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RISCV_TUNE("sifive-3-series", generic, rocket_tune_info)
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RISCV_TUNE("sifive-5-series", generic, rocket_tune_info)
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RISCV_TUNE("sifive-7-series", sifive_7, sifive_7_tune_info)
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+RISCV_TUNE("cva6", cva6, cva6_tune_info)
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RISCV_TUNE("thead-c906", generic, thead_c906_tune_info)
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RISCV_TUNE("size", generic, optimize_size_tune_info)
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diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
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index cf0cd669b..ff2a5ce33 100644
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--- a/gcc/config/riscv/riscv-opts.h
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+++ b/gcc/config/riscv/riscv-opts.h
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@@ -52,7 +52,8 @@ extern enum riscv_isa_spec_class riscv_isa_spec;
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/* Keep this list in sync with define_attr "tune" in riscv.md. */
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enum riscv_microarchitecture_type {
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generic,
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- sifive_7
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+ sifive_7,
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+ cva6
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};
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extern enum riscv_microarchitecture_type riscv_microarchitecture;
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diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
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index e88fa2d63..46a61b6b8 100644
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--- a/gcc/config/riscv/riscv.cc
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+++ b/gcc/config/riscv/riscv.cc
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@@ -339,6 +339,20 @@ static const struct riscv_tune_param sifive_7_tune_info = {
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true, /* slow_unaligned_access */
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};
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+/* Costs to use when optimizing for CVA6. */
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+static const struct riscv_tune_param cva6_tune_info = {
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+ {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_add */
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+ {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_mul */
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+ {COSTS_N_INSNS (20), COSTS_N_INSNS (20)}, /* fp_div */
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+ {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* int_mul */
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+ {COSTS_N_INSNS (6), COSTS_N_INSNS (6)}, /* int_div */
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+ 2, /* issue_rate */
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+ 6, /* branch_cost */
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+ 2, /* memory_cost */
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+ 8, /* fmv_cost */
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+ false, /* slow_unaligned_access */
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+};
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+
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/* Costs to use when optimizing for T-HEAD c906. */
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static const struct riscv_tune_param thead_c906_tune_info = {
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{COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_add */
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diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
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index bc384d9ae..f4dacff34 100644
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--- a/gcc/config/riscv/riscv.md
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+++ b/gcc/config/riscv/riscv.md
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@@ -437,7 +437,7 @@
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;; Microarchitectures we know how to tune for.
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;; Keep this in sync with enum riscv_microarchitecture.
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(define_attr "tune"
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- "generic,sifive_7"
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+ "generic,sifive_7,cva6"
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(const (symbol_ref "((enum attr_tune) riscv_microarchitecture)")))
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;; Describe a user's asm statement.
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@@ -3145,5 +3145,6 @@
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(include "pic.md")
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(include "generic.md")
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(include "sifive-7.md")
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+(include "cva6.md")
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(include "thead.md")
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(include "vector.md")

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