Commit c74e3ab
cache_subsys: cut timing path of AMOs with a buffer (#3341)
Recent ASIC synthesis with the CVA6+HPDcache exhibit a critical path concerning the response path for AMOs (Atomic Memory Operations) from the cache to the CVA6.
This PR adds a pipeline buffer into this path to enhance the timing (clock frequency). However, it increases the latency of AMOs by one cycle. This extra cycle is anyway acceptable as AMOs are not part of the the most frequent operations, and the clock frequency speedup largely compensates this.
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Signed-off-by: Cesar Fuguet <15080006+cfuguet@users.noreply.github.com>
Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>1 parent a1b3aed commit c74e3ab
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