Fix aes32esi bug (#3243)

The PR attempts to fix this aes32esi bug - which seems to be caused by orig_instr_o (raw instruction word) being assigned only if CVA6Cfg.CvxifEn || CVA6Cfg.RVF are enabled, though it's used downstream by the ZKN features as well (not only aes32esi, but also other instructions). I.e. the bug is manifested if ZKN is enabled, but CvxifEn and RVF are not; otherwise the AES implementation seems to work correctly.

Also because ZKN seems to depend on RVB being enabled as well, the PR also auto-enables RVB when ZKN is present (if it make sense a warning can be added in case it gets auto-enabled).


---------

Co-authored-by: JeanRochCoulon <jean-roch.coulon@thalesgroup.com>

Author: antonangeloff

core/decoder.sv

@@ -1846,7 +1846,7 @@ module decoder
     if (~ex_i.valid) begin
       // if we didn't already get an exception save the instruction here as we may need it
       // in the commit stage if we got a access exception to one of the CSR registers
-      if (CVA6Cfg.CvxifEn || CVA6Cfg.RVF)
+      if (CVA6Cfg.CvxifEn || CVA6Cfg.RVF || CVA6Cfg.ZKN)
         orig_instr_o = (is_compressed_i) ? {{CVA6Cfg.XLEN-16{1'b0}}, compressed_instr_i} : {{CVA6Cfg.XLEN-32{1'b0}}, instruction_i};
       if (CVA6Cfg.TvalEn)
         instruction_o.ex.tval  = (is_compressed_i) ? {{CVA6Cfg.XLEN-16{1'b0}}, compressed_instr_i} : {{CVA6Cfg.XLEN-32{1'b0}}, instruction_i};

core/include/build_config_pkg.sv

@@ -67,7 +67,7 @@ package build_config_pkg;
     cfg.XF16ALT = CVA6Cfg.XF16ALT;
     cfg.XF8 = CVA6Cfg.XF8;
     cfg.RVA = CVA6Cfg.RVA;
-    cfg.RVB = CVA6Cfg.RVB;
+    cfg.RVB = CVA6Cfg.RVB || CVA6Cfg.ZKN; // ZKN requires RVB
     cfg.ZKN = CVA6Cfg.ZKN;
     cfg.RVV = CVA6Cfg.RVV;
     cfg.RVC = CVA6Cfg.RVC;