Thank you note

[isa084]

Thanks to the support of the CVA6 maintainers, we were able to implement the following functionalities :

1. Simulation of RISC-V proxy kernel on CVA6 verilator model. This was merged into openhwgroup/cva6/master with Simulate veri-testharness with RISC-V proxy kernel #2900
2. Synthesis of openhwgroup/cva6 with yosys : Although not merged into upstream, this was a direct result of discussion on Open-source (yosys) synthesis of CVA6 (possible ?) #2975. I am currently maintaining a public repository containing the scripts for synthesis using yosys https://github.com/isa084/cva6-synthesis .

The above functionalities were crucial for the following publication from our research group :
https://cic.iacr.org/p/3/1/30/pdf

We also added an acknowledgement :

Special acknowledgement to @JeanRochCoulon @valentinThomazic @MikeOpenHWGroup for (1), and @xtofalex, @phsauter , @povik for (2).
Our research group at Bristol is currently working on multiple projects using CVA6.
Personally, I will be more than happy to extend my support in improving the OpenHWGroup ecosystem.

Thank you again.

[povik]

Thank you! I'm glad the tool was useful to your work.

[MikeOpenHWGroup]

I will be more than happy to extend my support in improving the OpenHWGroup ecosystem.

We would be more than happy to hear about your plans and to discuss this in more detail. Please reach out to me directly via email and we can discuss this further.

[isa084]

Hi @MikeOpenHWGroup , thanks a lot. I will send you an email within the next 3-4 days.

[valentinThomazic]

Hi @isa084
I am glad we proved to be helpful!
Thank you for your contributions and your work on the CVA6 project.