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Commit 19f9532

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Juan
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Adding support for Qmtech Kintex-7 dev board.
MIG .prj file was generated in Vivado. Digilent SD card Pmod is assumed in J13. Running at 40 MHz (not fully meeting constraints but boots without issues). Board: http://www.aliexpress.com/item/1005006765717166.html
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‎config/derivlist.txt‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -65,6 +65,9 @@ EXT_MEM_RANGE 64'h0FFFFFFF
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deriv fpgagenesys2 fpga
6666
EXT_MEM_RANGE 64'h3FFFFFFF
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deriv fpgaqmtechk7 fpga
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EXT_MEM_RANGE 64'h0FFFFFFF
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deriv fpgavcu108 fpga
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EXT_MEM_RANGE 64'h7FFFFFFF
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‎fpga/constraints/constraints-qmtechk7.xdc‎

Lines changed: 243 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,243 @@
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# The main clocks are all autogenerated by the Xilinx IP
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# mmcm_clkout0 is the clock output of the DDR3 memory interface / 4.
3+
# This clock is not used by wally or the AHB Bus. However it is used by the AXI BUS on the DD3 IP.
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create_generated_clock -name SPISDCClock -source [get_pins mmcm/clk_out3] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncoregen.uncore/sdc.sdc/SPICLK]
6+
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##### clock #####
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set_property LOC F22 [get_ports default_50mhz_clk]
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set_property IOSTANDARD LVCMOS33 [get_ports default_50mhz_clk]
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# Clocks and Resets (adjust to match board)
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set_property IOSTANDARD LVCMOS33 [get_ports default_200mhz_clk]
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set_property IOSTANDARD LVCMOS33 [get_ports resetn]
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set_property IOSTANDARD LVCMOS33 [get_ports south_reset]
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# Clock constraints
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create_clock -period 20.000 -name clk_50m [get_ports default_50mhz_clk]
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create_clock -period 5.000 -name sys_clk [get_ports sys_clk_i]
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create_clock -period 5.000 -name idelay_refclk [get_ports clk_ref_i]
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#create_clock -period 5.000 -name mig_clk_200m [get_ports sys_clk_i]
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set_property CLOCK_BUFFER_TYPE BUFG [get_nets wallypipelinedsoc/clk_out3_mmcm]
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# *** don't love this hack. RT: Don't understand why the recomemded input clock is causing a clock routing issue.
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set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets default_50mhz_clk]
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##### RVVI Ethernet (not working yet) ####
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set_property IOSTANDARD LVCMOS33 [get_ports {phy_txd[*] phy_tx_en}]
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set_property PACKAGE_PIN C16 [get_ports {phy_txd[0]}];
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set_property PACKAGE_PIN U24 [get_ports {phy_txd[1]}];
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set_property PACKAGE_PIN A20 [get_ports {phy_txd[2]}];
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set_property PACKAGE_PIN B20 [get_ports {phy_txd[3]}];
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set_property PACKAGE_PIN F20 [get_ports {phy_tx_en}]
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##### GPI ####
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set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { GPI[0] }] ; # GPIO4 on JP3
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set_property -dict { PACKAGE_PIN D21 IOSTANDARD LVCMOS33 PULLUP true } [get_ports { GPI[1] }] ; # GPIO5 on JP3
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set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { GPI[2] }]; # JP3 GPIO6
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set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { GPI[3] }]; # JP3 GPIO7
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set_input_delay -clock [get_clocks clk_out3_mmcm] -min -add_delay 0.000 [get_ports {GPI[*]}]
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set_input_delay -clock [get_clocks clk_out3_mmcm] -max -add_delay 0.000 [get_ports {GPI[*]}]
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set_max_delay -from [get_ports {GPI[*]}] 20.000
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##### GPO ####
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# User LEDs
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set_property -dict { PACKAGE_PIN R26 IOSTANDARD LVCMOS33 } [get_ports { GPO[0] }] ; # LED2
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set_property -dict { PACKAGE_PIN P26 IOSTANDARD LVCMOS33 } [get_ports { GPO[1] }] ; # LED3
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set_property -dict { PACKAGE_PIN N26 IOSTANDARD LVCMOS33 } [get_ports { GPO[2] }] ; # LED4
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# RPI connector pins
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set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { GPO[3] }];
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set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { GPO[4] }];
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set_max_delay -to [get_ports {GPO[*]}] 20.000
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set_output_delay -clock [get_clocks clk_out3_mmcm] -min -add_delay 0.000 [get_ports {GPO[*]}]
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set_output_delay -clock [get_clocks clk_out3_mmcm] -max -add_delay 0.000 [get_ports {GPO[*]}]
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##### UART #####
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# JP5 is on bank #14 (3.3V)
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set_property -dict { PACKAGE_PIN AE22 IOSTANDARD LVCMOS33 } [get_ports { UARTSout }]; #JP5, pin 7 (TX)
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set_property -dict { PACKAGE_PIN AF22 IOSTANDARD LVCMOS33 } [get_ports { UARTSin }]; #JP5, pin 8 (RX)
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set_input_delay -clock [get_clocks clk_out3_mmcm] -min -add_delay 0.000 [get_ports UARTSin]
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set_input_delay -clock [get_clocks clk_out3_mmcm] -max -add_delay 0.000 [get_ports UARTSin]
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set_output_delay -clock [get_clocks clk_out3_mmcm] -min -add_delay 0.000 [get_ports UARTSout]
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set_output_delay -clock [get_clocks clk_out3_mmcm] -max -add_delay 0.000 [get_ports UARTSout]
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##### reset #####
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#************** reset is inverted
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set_property -dict { PACKAGE_PIN V26 IOSTANDARD LVCMOS33 } [get_ports { south_reset }]; # SW2 on the board
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set_property -dict { PACKAGE_PIN U26 IOSTANDARD LVCMOS33 } [get_ports { resetn }]; # SW3 on the board
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set_input_delay -clock [get_clocks clk_out3_mmcm] -min -add_delay 2.000 [get_ports resetn]
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set_input_delay -clock [get_clocks clk_out3_mmcm] -max -add_delay 2.000 [get_ports resetn]
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set_max_delay -from [get_ports resetn] 20.000
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set_false_path -from [get_ports resetn]
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set_input_delay -clock [get_clocks clk_out3_mmcm] -min -add_delay 2.000 [get_ports south_reset]
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set_input_delay -clock [get_clocks clk_out3_mmcm] -max -add_delay 2.000 [get_ports south_reset]
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set_max_delay -from [get_ports south_reset] 20.000
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set_false_path -from [get_ports south_reset]
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##### SD Card I/O #####
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###########################################################################################
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# Digilent micro SD card PMOD (or equivalent) connected to J13
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###########################################################################################
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# pin selection
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set_property PACKAGE_PIN A24 [get_ports SDCCS]
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set_property PACKAGE_PIN B26 [get_ports SDCCmd]
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set_property PACKAGE_PIN D26 [get_ports SDCIn]
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set_property PACKAGE_PIN F25 [get_ports SDCCLK]
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set_property PACKAGE_PIN C26 [get_ports SDCCD]
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# NC
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set_property PACKAGE_PIN E26 [get_ports SDCWP]
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set_property PULLTYPE PULLUP [get_ports {SDCCS SDCIn SDCCD SDCWP SDCCmd}]
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set_property IOSTANDARD LVCMOS33 [get_ports {SDCCS SDCCmd SDCIn SDCCLK SDCCD SDCWP}]
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set_output_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCCS}]
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set_output_delay -clock [get_clocks SPISDCClock] -max -add_delay 10.000 [get_ports {SDCCS}]
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set_input_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.500 [get_ports {SDCIn}]
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set_input_delay -clock [get_clocks SPISDCClock] -max -add_delay 10.000 [get_ports {SDCIn}]
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set_output_delay -clock [get_clocks SPISDCClock] -min -add_delay 2.000 [get_ports {SDCCmd}]
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set_output_delay -clock [get_clocks SPISDCClock] -max -add_delay 6.000 [get_ports {SDCCmd}]
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### ddr3 ####
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[0]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[1]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[2]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[3]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[4]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[5]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[6]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[7]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[8]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[9]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[10]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[11]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[12]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[13]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[14]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[15]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[15]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[16]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[17]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[18]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[19]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[20]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[21]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[22]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[23]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[24]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[25]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[26]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[27]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[28]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[29]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[30]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[31]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[0]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[1]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[2]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[3]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[14]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[13]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[12]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[11]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[10]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[9]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[8]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[7]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[6]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[5]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[4]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[3]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[2]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[1]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[0]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[2]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[1]}]
165+
set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[0]}]
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set_property IOSTANDARD DIFF_SSTL15_DCI [get_ports ddr3_ck_p[0]]
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set_property IOSTANDARD DIFF_SSTL15_DCI [get_ports ddr3_ck_n[0]]
168+
set_property IOSTANDARD SSTL15 [get_ports ddr3_ras_n]
169+
set_property IOSTANDARD SSTL15 [get_ports ddr3_cas_n]
170+
set_property IOSTANDARD SSTL15 [get_ports ddr3_we_n]
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set_property IOSTANDARD SSTL15 [get_ports ddr3_reset_n]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_cke[0]}]
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set_property IOSTANDARD SSTL15 [get_ports {ddr3_odt[0]}]
174+
# DDR3 CS not driven in this board
175+
set_property IOSTANDARD SSTL15 [get_ports ddr3_cs_n*]
176+
set_property LOC AC12 [get_ports ddr3_cs_n*]
177+
178+
set_property INTERNAL_VREF 0.75 [get_iobanks 34]
179+
set_property INTERNAL_VREF 0.90 [get_iobanks 33]
180+
181+
set_property PACKAGE_PIN AF5 [get_ports ddr3_addr[0]]
182+
set_property PACKAGE_PIN AF2 [get_ports ddr3_addr[1]]
183+
set_property PACKAGE_PIN AD6 [get_ports ddr3_addr[2]]
184+
set_property PACKAGE_PIN AC6 [get_ports ddr3_addr[3]]
185+
set_property PACKAGE_PIN AD4 [get_ports ddr3_addr[4]]
186+
set_property PACKAGE_PIN AB6 [get_ports ddr3_addr[5]]
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set_property PACKAGE_PIN AE2 [get_ports ddr3_addr[6]]
188+
set_property PACKAGE_PIN Y5 [get_ports ddr3_addr[7]]
189+
set_property PACKAGE_PIN AA4 [get_ports ddr3_addr[8]]
190+
set_property PACKAGE_PIN AE6 [get_ports ddr3_addr[9]]
191+
set_property PACKAGE_PIN AE3 [get_ports ddr3_addr[10]]
192+
set_property PACKAGE_PIN AD5 [get_ports ddr3_addr[11]]
193+
set_property PACKAGE_PIN AB4 [get_ports ddr3_addr[12]]
194+
set_property PACKAGE_PIN Y6 [get_ports ddr3_addr[13]]
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196+
set_property PACKAGE_PIN AD3 [get_ports ddr3_ba[0]]
197+
set_property PACKAGE_PIN AE1 [get_ports ddr3_ba[1]]
198+
set_property PACKAGE_PIN AE5 [get_ports ddr3_ba[2]]
199+
200+
set_property PACKAGE_PIN AC4 [get_ports ddr3_cas_n]
201+
202+
set_property PACKAGE_PIN AB5 [get_ports ddr3_ck_n[0]]
203+
set_property PACKAGE_PIN AA5 [get_ports ddr3_ck_p[0]]
204+
set_property PACKAGE_PIN AD1 [get_ports ddr3_cke[0]]
205+
set_property PACKAGE_PIN V1 [get_ports ddr3_dm[0]]
206+
set_property PACKAGE_PIN V3 [get_ports ddr3_dm[1]]
207+
set_property PACKAGE_PIN W1 [get_ports ddr3_dq[0]]
208+
set_property PACKAGE_PIN V2 [get_ports ddr3_dq[1]]
209+
set_property PACKAGE_PIN Y1 [get_ports ddr3_dq[2]]
210+
set_property PACKAGE_PIN Y3 [get_ports ddr3_dq[3]]
211+
set_property PACKAGE_PIN AC2 [get_ports ddr3_dq[4]]
212+
set_property PACKAGE_PIN Y2 [get_ports ddr3_dq[5]]
213+
set_property PACKAGE_PIN AB2 [get_ports ddr3_dq[6]]
214+
set_property PACKAGE_PIN AA3 [get_ports ddr3_dq[7]]
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set_property PACKAGE_PIN U1 [get_ports ddr3_dq[8]]
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set_property PACKAGE_PIN V4 [get_ports ddr3_dq[9]]
217+
set_property PACKAGE_PIN U6 [get_ports ddr3_dq[10]]
218+
set_property PACKAGE_PIN W3 [get_ports ddr3_dq[11]]
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set_property PACKAGE_PIN V6 [get_ports ddr3_dq[12]]
220+
set_property PACKAGE_PIN U2 [get_ports ddr3_dq[13]]
221+
set_property PACKAGE_PIN U7 [get_ports ddr3_dq[14]]
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set_property PACKAGE_PIN U5 [get_ports ddr3_dq[15]]
223+
224+
set_property PACKAGE_PIN AF3 [get_ports ddr3_odt[0]]
225+
set_property PACKAGE_PIN AC3 [get_ports ddr3_ras_n]
226+
set_property W4 [get_ports ddr3_reset_n]
227+
set_property PACKAGE_PIN AF4 [get_ports ddr3_we_n]
228+
229+
reset_property IOSTANDARD [get_ports {ddr3_dqs_*[*]}]
230+
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[*]}]
231+
set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[*]}]
232+
set_property DIFF_TERM TRUE [get_ports {ddr3_dqs_p[*]}]
233+
set_property DIFF_TERM TRUE [get_ports {ddr3_dqs_n[*]}]
234+
set_property DIFF_PAIR ddr3_dqs_p[0] [get_ports {ddr3_dqs_n[0]}]
235+
set_property DIFF_PAIR ddr3_dqs_p[1] [get_ports {ddr3_dqs_n[1]}]
236+
set_property SLEW FAST [get_ports {ddr3_dqs_p[*] ddr3_dqs_n[*]}]
237+
set_property PACKAGE_PIN AC1 [get_ports {ddr3_dqs_n[0]}]
238+
set_property PACKAGE_PIN W5 [get_ports {ddr3_dqs_n[1]}]
239+
set_property PACKAGE_PIN AB1 [get_ports {ddr3_dqs_p[0]}]
240+
set_property PACKAGE_PIN W6 [get_ports {ddr3_dqs_p[1]}]
241+
242+
243+
set_max_delay -datapath_only -from [get_pins xlnx_ddr3_c0/u_xlnx_ddr3_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/init_calib_complete_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 20.000

‎fpga/generator/Makefile‎

Lines changed: 24 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@ dst := IP
22

33
all: ArtyA7
44

5-
.PHONY: ArtyA7 vcu118 vcu108 genesys2
5+
.PHONY: ArtyA7 vcu118 vcu108 genesys2 qmtechk7
66

77
ArtyA7: export XILINX_PART := xc7a100tcsg324-1
88
ArtyA7: export XILINX_BOARD := digilentinc.com:arty-a7-100:part0:1.1
@@ -32,13 +32,21 @@ genesys2: export SYSTEMCLOCK := 40000000
3232
genesys2: export MAXSDCCLOCK := 10000000
3333
genesys2: FPGA_GENESYS2
3434

35+
qmtechk7: export XILINX_PART := xc7k325tffg676-1
36+
# Not really a board from Xilinx
37+
qmtechk7: export XILINX_BOARD := qmtechk7
38+
qmtechk7: export board := qmtechk7
39+
qmtechk7: export SYSTEMCLOCK := 40000000
40+
qmtechk7: export MAXSDCCLOCK := 10000000
41+
qmtechk7: FPGA_QMTECHK7
42+
3543
# variables computed from config
3644
EXT_MEM_BASE = $(shell grep 'EXT_MEM_BASE' ../../config/deriv/fpga$(board)/config.vh | sed 's/.*=.*h\([[:alnum:]]*\);/0x\1/g')
3745

3846
EXT_MEM_RANGE = $(shell grep 'EXT_MEM_RANGE' ../../config/deriv/fpga$(board)/config.vh | sed 's/.*=.*h\([[:alnum:]]*\);/\1/g' | sed 's/\(.*\)/base=16;\1+1/g' | bc | sed 's/\(.*\)/0x\1/g')
3947

4048

41-
.PHONY: FPGA_Arty FPGA_VCU
49+
.PHONY: FPGA_Arty FPGA_VCU FPGA_QMTECHK7
4250
FPGA_Arty: PreProcessFiles IP_Arty zsbl
4351
vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log
4452
FPGA_VCU: PreProcessFiles IP_VCU zsbl
@@ -47,8 +55,11 @@ FPGA_VCU: PreProcessFiles IP_VCU zsbl
4755
FPGA_GENESYS2: PreProcessFiles IP_GENESYS2 zsbl
4856
vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log
4957

58+
FPGA_QMTECHK7: PreProcessFiles IP_QMTECHK7 zsbl
59+
vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log
60+
5061
# Generate IP Blocks
51-
.PHONY: IP_Arty IP_VCU
62+
.PHONY: IP_Arty IP_VCU IP_QMTECHK7
5263
IP_VCU: $(dst)/sysrst.log \
5364
MEM_VCU \
5465
$(dst)/clkconverter.log \
@@ -65,8 +76,14 @@ IP_GENESYS2: $(dst)/sysrst.log \
6576
$(dst)/clkconverter.log \
6677
$(dst)/ahbaxibridge.log
6778

79+
IP_QMTECHK7: $(dst)/sysrst.log \
80+
MEM_QMTECHK7 \
81+
$(dst)/mmcm-qmtechk7.log \
82+
$(dst)/clkconverter.log \
83+
$(dst)/ahbaxibridge.log
84+
6885
# Generate Memory IP Blocks
69-
.PHONY: MEM_VCU MEM_Arty
86+
.PHONY: MEM_VCU MEM_Arty MEM_QMTECHK7
7087
MEM_VCU:
7188
$(MAKE) $(dst)/ddr4-$(board).log
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MEM_Arty:
@@ -75,6 +92,9 @@ MEM_Arty:
7592
MEM_GENESYS2:
7693
$(MAKE) $(dst)/ddr3-$(board).log
7794

95+
MEM_QMTECHK7:
96+
$(MAKE) $(dst)/ddr3-$(board).log
97+
7898
# Copy files and make necessary modifications
7999
.PHONY: PreProcessFiles
80100
PreProcessFiles:

‎fpga/generator/ahbaxibridge.tcl‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@ set boardName $::env(XILINX_BOARD)
55
set ipName ahbaxibridge
66

77
create_project $ipName . -force -part $partNumber
8-
if {$boardName!="ArtyA7"} {
8+
if {$boardName!="ArtyA7" && $boardName!="qmtechk7"} {
99
set_property board_part $boardName [current_project]
1010
}
1111

‎fpga/generator/clkconverter.tcl‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@ set boardName $::env(XILINX_BOARD)
77
set ipName clkconverter
88

99
create_project $ipName . -force -part $partNumber
10-
if {$boardName!="ArtyA7"} {
10+
if {$boardName!="ArtyA7" && $boardName!="qmtechk7"} {
1111
set_property board_part $boardName [current_project]
1212
}
1313

‎fpga/generator/ddr3-qmtechk7.tcl‎

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,20 @@
1+
set partNumber $::env(XILINX_PART)
2+
set boardName $::env(XILINX_BOARD)
3+
4+
set ipName ddr3
5+
6+
create_project $ipName . -force -part $partNumber
7+
8+
create_ip -name mig_7series -vendor xilinx.com -library ip -module_name $ipName
9+
10+
exec mkdir -p IP/$ipName.srcs/sources_1/ip/$ipName
11+
exec cp ../xlnx_ddr3-qmtechk7-mig.prj $ipName.srcs/sources_1/ip/$ipName/xlnx_ddr3-qmtechk7-mig.prj
12+
13+
set_property -dict [list CONFIG.XML_INPUT_FILE {xlnx_ddr3-qmtechk7-mig.prj} CONFIG.RESET_BOARD_INTERFACE {Custom} CONFIG.MIG_DONT_TOUCH_PARAM {Custom} CONFIG.BOARD_MIG_PARAM {Custom}] [get_ips $ipName]
14+
15+
generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
16+
generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
17+
create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
18+
launch_run -jobs 8 ${ipName}_synth_1
19+
wait_on_run ${ipName}_synth_1
20+

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