@@ -104,18 +104,21 @@ module hptw import cvw::*; #(parameter cvw_t P) (
104104 logic HPTWAccessFaultDelay;
105105 logic TakeHPTWFault;
106106 logic PBMTFaultM;
107+ logic DAUFaultM;
108+ logic PBMTOrDAUFaultM;
107109 logic HPTWFaultM;
108110 logic ResetPTE;
109111
110112 // map hptw access faults onto either the original LSU load/store fault or instruction access fault
111113 assign LSUAccessFaultM = LSULoadAccessFaultM | LSUStoreAmoAccessFaultM;
112- assign HPTWFaultM = LSUAccessFaultM | PBMTFaultM;
114+ assign PBMTOrDAUFaultM = PBMTFaultM | DAUFaultM;
115+ assign HPTWFaultM = LSUAccessFaultM | PBMTOrDAUFaultM;
113116 assign HPTWLoadAccessFault = LSUAccessFaultM & DTLBWalk & MemRWM[1 ] & ~ MemRWM[0 ];
114117 assign HPTWStoreAmoAccessFault = LSUAccessFaultM & DTLBWalk & MemRWM[0 ];
115118 assign HPTWInstrAccessFault = LSUAccessFaultM & ~ DTLBWalk;
116- assign HPTWLoadPageFault = PBMTFaultM & DTLBWalk & MemRWM[1 ] & ~ MemRWM[0 ];
117- assign HPTWStoreAmoPageFault = PBMTFaultM & DTLBWalk & MemRWM[0 ];
118- assign HPTWInstrPageFault = PBMTFaultM & ~ DTLBWalk;
119+ assign HPTWLoadPageFault = PBMTOrDAUFaultM & DTLBWalk & MemRWM[1 ] & ~ MemRWM[0 ];
120+ assign HPTWStoreAmoPageFault = PBMTOrDAUFaultM & DTLBWalk & MemRWM[0 ];
121+ assign HPTWInstrPageFault = PBMTOrDAUFaultM & ~ DTLBWalk;
119122
120123 flopr # (6 ) HPTWAccesFaultReg (clk, reset, { HPTWLoadAccessFault, HPTWStoreAmoAccessFault, HPTWInstrAccessFault,
121124 HPTWLoadPageFault, HPTWStoreAmoPageFault, HPTWInstrPageFault} ,
@@ -155,6 +158,7 @@ module hptw import cvw::*; #(parameter cvw_t P) (
155158 assign ValidNonLeafPTE = Valid & ~ LeafPTE;
156159 if (P .XLEN == 64 ) assign PBMTFaultM = ValidNonLeafPTE & (| PTE [62 : 61 ]);
157160 else assign PBMTFaultM = 1'b0 ;
161+ assign DAUFaultM = ValidNonLeafPTE & (| PTE [7 : 6 ] | PTE [4 ]);
158162
159163 if (P .SVADU_SUPPORTED ) begin : hptwwrites
160164 logic ReadAccess, WriteAccess;
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