tcl/target/gd32vf103: adjust reset workaround to new riscv target

Configure reset-start event to set/clear DM resethaltreq bit.

In reset-assert event check if srst is configured.
Avoid unnecessary double reset if srst is configured.

Write dmcontrol ackhavereset in reset-deassert-post event if necessary.

Change-Id: I06b201bc5651c301912158c1436b9b3e3bc042a0
Signed-off-by: Tomas Vanek <[email protected]>
Reviewed-on: https://review.openocd.org/c/openocd/+/9316
Reviewed-by: Tom Hebb <[email protected]>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <[email protected]>

Author: tom-van

tcl/target/gd32vf103.cfg

@@ -56,6 +56,24 @@ $_TARGETNAME configure -event reset-init {
 	mmw 0xE0042004 0x00000300 0
 }
 
+set dmcontrol 			0x10
+set dmcontrol_dmactive	[expr {1 << 0}]
+set dmcontrol_clrresethaltreq [expr {1 << 2}]
+set dmcontrol_setresethaltreq [expr {1 << 3}]
+set dmcontrol_ackhavereset [expr {1 << 28}]
+set dmstatus 			0x11
+set dmstatus_allunavail [expr {1 << 12}]
+set dmstatus_allhavereset [expr {1 << 19}]
+
+$_TARGETNAME configure -event reset-start {
+	if {$halt} {
+		set ctrl [expr {$::dmcontrol_dmactive | $::dmcontrol_setresethaltreq}]
+	} else {
+		set ctrl [expr {$::dmcontrol_dmactive | $::dmcontrol_clrresethaltreq}]
+	}
+	riscv dmi_write $::dmcontrol $ctrl
+}
+
 # On this chip, ndmreset (the debug module bit that triggers a software reset)
 # doesn't work. So for JTAG connections without an SRST, we need to trigger a
 # reset manually. This is an undocumented reset sequence that's used by the
@@ -64,42 +82,19 @@ $_TARGETNAME configure -event reset-init {
 #   https://github.com/sipeed/platform-gd32v/commit/f9cbb44819bc05dd2010cc815c32be0486800cc2
 #
 $_TARGETNAME configure -event reset-assert {
-	set dmcontrol 		0x10
-	set dmcontrol_dmactive	[expr {1 << 0}]
-	set dmcontrol_ackhavereset [expr {1 << 28}]
-	set dmcontrol_haltreq	[expr {1 << 31}]
-
-	global _RESETMODE
-
-	# If hardware NRST signal is connected and configured (reset_config srst_only)
-	# the device has been recently reset in 'jtag arp_init-reset', therefore
-	# DM_DMSTATUS_ANYHAVERESET reads 1.
-	# The following 'halt' command checks this status bit
-	# and shows 'Hart 0 unexpectedly reset!' if set.
-	# Prevent this message by sending an acknowledge first.
-	set val [expr {$dmcontrol_dmactive | $dmcontrol_ackhavereset}]
-	riscv dmi_write $dmcontrol $val
+	set reset_config_options [reset_config]
+	# If hardware NRST signal is connected and configured, reset has been
+	# triggered. Avoid second reset and return early
+	if {[string match {srst_only *} $reset_config_options]
+			|| [string match {srst_and_trst *} $reset_config_options]} {
+		return
+	}
 
 	# Halt the core so that we can write to memory. We do this first so
 	# that it doesn't clobber our dmcontrol configuration.
 	halt
 
-	# Set haltreq appropriately for the type of reset we're doing. This
-	# replicates what the generic RISC-V reset_assert() function would
-	# do if we weren't overriding it. The $_RESETMODE hack sucks, but
-	# it's the least invasive way to determine whether we need to halt.
-	#
-	# If we didn't override the generic handler, we'd actually still have
-	# to do this: the default handler sets ndmreset, which prevents memory
-	# access even though it doesn't actually trigger a reset on this chip.
-	# So we'd need to unset it here, which involves a write to dmcontrol,
-	# Since haltreq is write-only and there's no way to leave it unchanged,
-	# we'd have to figure out its proper value anyway.
-	set val $dmcontrol_dmactive
-	if {$halt} {
-		set val [expr {$val | $dmcontrol_haltreq}]
-	}
-	riscv dmi_write $dmcontrol $val
+	echo "gd32vf103 reset workaround halt=$halt"
 
 	# Unlock 0xe0042008 so that the next write triggers a reset
 	mww 0xe004200c 0x4b5a6978
@@ -122,12 +117,21 @@ $_TARGETNAME configure -event reset-assert {
 # lowered in the main deassert_reset procedure, we wait for the absence of the
 # unavailable state.
 $_TARGETNAME configure -event reset-deassert-post {
-	set timeout_s 2
-	set start [clock seconds]
-	# dmstatus address is 0x11, allunavail is the 12th bit
-	while {[riscv dmi_read 0x11] & 1 << 12} {
-		if {[clock seconds] - $start > $timeout_s} {
+	set timeout_ms 100
+	set start [clock milliseconds]
+	while {1} {
+		set status [riscv dmi_read $::dmstatus]
+		if {!($status & $::dmstatus_allunavail)} {
+			break
+		}
+		if {[clock milliseconds] - $start > $timeout_ms} {
 			error {Timed out waiting for the hart to become available after a reset}
 		}
 	}
+
+	set ctrl [expr {$::dmcontrol_dmactive | $::dmcontrol_clrresethaltreq}]
+	if {$status & $::dmstatus_allhavereset} {
+		set ctrl [expr {$ctrl | $::dmcontrol_ackhavereset}]
+	}
+	riscv dmi_write $::dmcontrol $ctrl
 }