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Merge branch 'main' into PR-28-modify-full-speed-signal-gen-to-remove-the-ddss-for-baseband-pulses-generation-and-save-bram-resources
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docs/topics/index.rst

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Original file line numberDiff line numberDiff line change
@@ -11,3 +11,4 @@ Specific topics
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gen_config
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units
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changing_fs
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reference_clock

docs/topics/reference_clock.rst

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Reference clock generation
2+
==========================
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It's an advantage of the RFSoC that all of the DAC and ADC clocks are synthesized from a common reference and are always phase-locked with respect to each other.
5+
This reference is generated by dedicated clock synthesizer chips which are normally locked to an on-board reference oscillator.
6+
The on-board oscillator is pretty good (sub-ppm stability, check the board schematics), better than the linewidths of most devices.
7+
8+
The clock chips are configured the first time you initialize :class:`.QickSoc()` after powering on your board; after that, they are normally only reconfigured if you are specifying a certain configuration (such as external clock, see below).
9+
You will see some LEDs come on when the clocks are configured; they should then stay on continously without flickering, except when reconfigured.
10+
On the ZCU216/ZCU208, the clock chips and their status LEDs are on the CLK104 daughterboard. For the other boards, the clock chips and LEDs are on the main board.
11+
12+
* ZCU111: four LEDs in a row, labeled "4208 STATUS" and "MUXOUT RF1/2/3"
13+
* ZCU216/ZCU208: the clock chips and LEDs are on the CLK104 daughterboard; one LED is a power indicator and three are status
14+
* RFSoC4x2: four LEDs in a row, labeled "CLOCK STATUS"
15+
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External clock
17+
--------------
18+
19+
You might want to lock your board to an external clock source for two reasons:
20+
21+
* Frequency stability: the on-board reference oscillator is good but not perfect.
22+
If you play a continuous tone from a DAC into a spectrum analyzer and put your finger on the oscillator's metal can, you will see the frequency shift by hundreds of Hz.
23+
You might need better stability, such as what you get from a rubidium reference.
24+
* Synchronization: you may need the RFSoC to be phase- or frequency-locked to other instrumentation or other RFSoCs.
25+
26+
QICK, and all of the supported RFSoC boards, accept an external reference clock.
27+
To make your board lock to a reference, use the ``external_clk=True`` argument to :class:`.QickSoc()`.
28+
See the API documentation for the connector and the needed frequency.
29+
To figure out the needed power in whatever unit makes sense to you, the input circuit is as follows:
30+
31+
* ZCU111: 3 dB attenuator to single-ended AC-coupled LMK04208 input.
32+
* ZCU216/ZCU208 (the clock references are on the CLK104 daughterboard): 3 dB attenuator to single-ended AC-coupled LMK04828B input.
33+
* RFSoC4x2: no attenuation, to single-ended AC-coupled LMK04828B input.
34+
35+
The LMK04208/LMK04828B data sheets specify an input signal of 0.25/0.35 to 2.4 Vpp. You can work out the details, but 0-10 dBm is a safe range.
36+
37+
There is also an ``clk_output=True`` argument that you can use to output a reference signal (you can use this independently of whether you're using an external clock).
38+
This is at a frequency that's not likely to be useful to you, except as a way to monitor the lock.

firmware/ip/qick_processor/component.xml

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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>viewChecksum</spirit:name>
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<spirit:value>203158e2</spirit:value>
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<spirit:value>b6bbf956</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
@@ -2255,7 +2255,7 @@
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>viewChecksum</spirit:name>
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<spirit:value>203158e2</spirit:value>
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<spirit:value>b6bbf956</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
@@ -2284,7 +2284,7 @@
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>viewChecksum</spirit:name>
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<spirit:value>8738b4a6</spirit:value>
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<spirit:value>4ab07b4f</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
@@ -6487,7 +6487,7 @@
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<spirit:file>
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<spirit:name>xgui/qick_processor_v2_0.tcl</spirit:name>
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<spirit:fileType>tclSource</spirit:fileType>
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<spirit:userFileType>CHECKSUM_8738b4a6</spirit:userFileType>
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<spirit:userFileType>CHECKSUM_4ab07b4f</spirit:userFileType>
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<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
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</spirit:file>
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</spirit:fileSet>
@@ -6511,7 +6511,7 @@
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</spirit:parameter>
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<spirit:parameter>
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<spirit:name>REG_AW</spirit:name>
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<spirit:displayName>General Purpouse Register Address Width</spirit:displayName>
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<spirit:displayName>General Purpose Register Address Width</spirit:displayName>
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<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.REG_AW" spirit:minimum="3" spirit:maximum="5" spirit:rangeType="long">4</spirit:value>
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</spirit:parameter>
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<spirit:parameter>
@@ -6631,42 +6631,17 @@
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</spirit:parameters>
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<spirit:vendorExtensions>
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<xilinx:coreExtensions>
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<xilinx:supportedFamilies>
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<xilinx:family xilinx:lifeCycle="Production">virtex7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">qvirtex7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">versal</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">kintex7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">kintex7l</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">qkintex7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">qkintex7l</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">akintex7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">artix7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">artix7l</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">aartix7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">qartix7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">qzynq</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">azynq</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">spartan7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">aspartan7</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">virtexu</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">zynquplus</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">virtexuplus</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">virtexuplusHBM</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">virtexuplus58g</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">kintexuplus</xilinx:family>
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<xilinx:family xilinx:lifeCycle="Production">kintexu</xilinx:family>
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</xilinx:supportedFamilies>
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<xilinx:taxonomies>
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<xilinx:taxonomy>/UserIP</xilinx:taxonomy>
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</xilinx:taxonomies>
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<xilinx:displayName>qick_processor</xilinx:displayName>
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<xilinx:autoFamilySupportLevel>level_2</xilinx:autoFamilySupportLevel>
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<xilinx:definitionSource>package_project</xilinx:definitionSource>
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<xilinx:coreRevision>23</xilinx:coreRevision>
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<xilinx:coreRevision>24</xilinx:coreRevision>
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<xilinx:upgrades>
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<xilinx:canUpgradeFrom>user.org:user:axis_tproc_B:1.0</xilinx:canUpgradeFrom>
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</xilinx:upgrades>
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<xilinx:coreCreationDateTime>2025-03-31T21:28:59Z</xilinx:coreCreationDateTime>
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<xilinx:coreCreationDateTime>2025-06-05T23:02:03Z</xilinx:coreCreationDateTime>
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<xilinx:tags>
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<xilinx:tag xilinx:name="ui.data.coregen.dd@648bece3_ARCHIVE_LOCATION">/home/mdifeder/Projects/20.2/IPs/TPROCB_1</xilinx:tag>
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<xilinx:tag xilinx:name="ui.data.coregen.dd@7858384c_ARCHIVE_LOCATION">/home/mdifeder/Projects/20.2/IPs/TPROCB_1</xilinx:tag>
@@ -7509,10 +7484,10 @@
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<xilinx:xilinxVersion>2023.1</xilinx:xilinxVersion>
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<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="2897c82e"/>
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<xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="769c350d"/>
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<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="8c3df720"/>
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<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="760adee5"/>
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<xilinx:checksum xilinx:scope="ports" xilinx:value="f423e66e"/>
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<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="0a52d470"/>
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<xilinx:checksum xilinx:scope="parameters" xilinx:value="18f0ddd6"/>
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<xilinx:checksum xilinx:scope="parameters" xilinx:value="4960cdd2"/>
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</xilinx:packagingInfo>
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</spirit:vendorExtensions>
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</spirit:component>

firmware/ip/qick_processor/src/dsp_macro_0/dsp_macro_0.xci

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@@ -154,7 +154,7 @@
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},
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"project_parameters": {
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"ARCHITECTURE": [ { "value": "zynquplusRFSOC" } ],
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"BASE_BOARD_PART": [ { "value": "xilinx.com:zcu216:part0:2.0" } ],
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"BASE_BOARD_PART": [ { "value": "" } ],
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"BOARD_CONNECTIONS": [ { "value": "" } ],
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"DEVICE": [ { "value": "xczu49dr" } ],
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"PACKAGE": [ { "value": "ffvf1760" } ],
@@ -710,4 +710,4 @@
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}
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}
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}
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}
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}

firmware/ip/qick_processor/src/qick_processor.sv

Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -183,8 +183,6 @@ qproc_ctrl # (
183183
.t_rst_ni ( t_rst_ni ),
184184
.c_clk_i ( c_clk_i ),
185185
.c_rst_ni ( c_rst_ni ),
186-
.ps_clk_i ( ps_clk_i ),
187-
.ps_rst_ni ( ps_rst_ni ),
188186
.proc_start_i ( proc_start_i ),
189187
.proc_stop_i ( proc_stop_i ),
190188
.core_start_i ( core_start_i ),
@@ -195,8 +193,10 @@ qproc_ctrl # (
195193
.int_time_en ( int_time_pen ),
196194
.int_time_cmd ( core_usr_operation[3:0] ),
197195
.int_time_dt ( core_usr_b_dt ),
198-
.xreg_TPROC_CTRL ( xreg_TPROC_CTRL ),
199-
.xreg_TPROC_CFG ( xreg_TPROC_CFG ),
196+
.PS_TPROC_CTRL ( xreg_TPROC_CTRL ),
197+
.PS_TPROC_CFG ( xreg_TPROC_CFG[10:9]),
198+
// .xreg_TPROC_CTRL ( xreg_TPROC_CTRL ),
199+
// .xreg_TPROC_CFG ( xreg_TPROC_CFG ),
200200
.xreg_TPROC_W_DT ( xreg_TPROC_W_DT[0] ),
201201
.all_fifo_full_i ( all_fifo_full ),
202202
.core_rst_o ( core_rst ),
@@ -410,8 +410,6 @@ qproc_mem_ctrl # (
410410
qproc_axi_reg QPROC_xREG (
411411
.ps_aclk ( ps_clk_i ) ,
412412
.ps_aresetn ( ps_rst_ni ) ,
413-
.c_clk_i ( c_clk_i ) ,
414-
.c_rst_ni ( c_rst_ni ) ,
415413
.IF_s_axireg ( IF_s_axireg ) ,
416414
.TPROC_CTRL ( xreg_TPROC_CTRL ) ,
417415
.TPROC_CFG ( xreg_TPROC_CFG ) ,
@@ -428,6 +426,7 @@ qproc_axi_reg QPROC_xREG (
428426
.TIME_USR ( c_time_usr ) ,
429427
.TPROC_STATUS ( xreg_TPROC_STATUS ) ,
430428
.TPROC_DEBUG ( xreg_TPROC_DEBUG ) );
429+
431430
// AXI_REG TPROC_R_DT source selection
432431
///////////////////////////////////////////////////////////////////////////////
433432
wire [ 3:0] tproc_src_dt;

firmware/ip/qick_processor/src/qproc_axi_reg.sv

Lines changed: 43 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -5,28 +5,28 @@
55
module qproc_axi_reg(
66
input wire ps_aclk ,
77
input wire ps_aresetn ,
8-
input wire c_clk_i ,
9-
input wire c_rst_ni ,
8+
// input wire c_clk_i ,
9+
// input wire c_rst_ni ,
1010
TYPE_IF_AXI_REG.slave IF_s_axireg ,
11-
output wire [15:0] TPROC_CTRL ,
12-
output reg [15:0] TPROC_CFG ,
13-
output reg [15:0] MEM_ADDR ,
14-
output reg [15:0] MEM_LEN ,
15-
output reg [31:0] MEM_DT_I ,
16-
output reg [31:0] TPROC_W_DT1 ,
17-
output reg [31:0] TPROC_W_DT2 ,
18-
output reg [7:0] CORE_CFG ,
19-
output reg [7:0] READ_SEL ,
20-
input reg [31:0] MEM_DT_O ,
21-
input reg [31:0] TPROC_R_DT1 ,
22-
input reg [31:0] TPROC_R_DT2 ,
23-
input reg [31:0] TIME_USR ,
24-
input reg [31:0] TPROC_STATUS ,
25-
input reg [31:0] TPROC_DEBUG
26-
);
11+
output logic [15:0] TPROC_CTRL ,
12+
output logic [15:0] TPROC_CFG ,
13+
output logic [15:0] MEM_ADDR ,
14+
output logic [15:0] MEM_LEN ,
15+
output logic [31:0] MEM_DT_I ,
16+
output logic [31:0] TPROC_W_DT1 ,
17+
output logic [31:0] TPROC_W_DT2 ,
18+
output logic [7:0] CORE_CFG ,
19+
output logic [7:0] READ_SEL ,
20+
input wire [31:0] MEM_DT_O ,
21+
input wire [31:0] TPROC_R_DT1 ,
22+
input wire [31:0] TPROC_R_DT2 ,
23+
input wire [31:0] TIME_USR ,
24+
input wire [31:0] TPROC_STATUS ,
25+
input wire [31:0] TPROC_DEBUG
26+
);
2727

2828

29-
wire [15:0] PS_TPROC_CTRL, PS_TPROC_CFG;
29+
// wire [15:0] PS_TPROC_CTRL, PS_TPROC_CFG;
3030

3131
// AXI Slave.
3232
axi_slv_qproc QPROC_xREG (
@@ -51,8 +51,8 @@ axi_slv_qproc QPROC_xREG (
5151
.rresp ( IF_s_axireg.axi_rresp ) ,
5252
.rvalid ( IF_s_axireg.axi_rvalid ) ,
5353
.rready ( IF_s_axireg.axi_rready ) ,
54-
.TPROC_CTRL ( PS_TPROC_CTRL ) ,
55-
.TPROC_CFG ( PS_TPROC_CFG ) ,
54+
.TPROC_CTRL ( TPROC_CTRL ) ,
55+
.TPROC_CFG ( TPROC_CFG ) ,
5656
.MEM_ADDR ( MEM_ADDR ) ,
5757
.MEM_LEN ( MEM_LEN ) ,
5858
.MEM_DT_I ( MEM_DT_I ) ,
@@ -67,26 +67,29 @@ axi_slv_qproc QPROC_xREG (
6767
.TPROC_STATUS ( TPROC_STATUS ) ,
6868
.TPROC_DEBUG ( TPROC_DEBUG ) );
6969

70-
71-
reg [15:0] tproc_ctrl_rcd, tproc_ctrl_r, tproc_ctrl_2r;
72-
reg [15:0] tproc_cfg_rcd;
70+
//-------------------------------------------------------
71+
// Moved to qproc_ctrl due to issue #33
7372

74-
// From PS_CLK to C_CLK
75-
always_ff @(posedge c_clk_i)
76-
if (!c_rst_ni) begin
77-
tproc_ctrl_rcd <= 0 ;
78-
tproc_ctrl_r <= 0 ;
79-
tproc_ctrl_2r <= 0 ;
80-
tproc_cfg_rcd <= 0 ;
81-
end else begin
82-
tproc_ctrl_rcd <= PS_TPROC_CTRL ;
83-
tproc_ctrl_r <= tproc_ctrl_rcd ;
84-
tproc_ctrl_2r <= tproc_ctrl_r ;
85-
tproc_cfg_rcd <= PS_TPROC_CFG ;
86-
TPROC_CFG <= tproc_cfg_rcd ;
87-
end
73+
// reg [15:0] tproc_ctrl_rcd, tproc_ctrl_r, tproc_ctrl_2r;
74+
// reg [15:0] tproc_cfg_rcd;
8875

89-
// The C_TPROC_CTRL is only ONE clock.
90-
assign TPROC_CTRL = tproc_ctrl_r & ~tproc_ctrl_2r ;
76+
// // From PS_CLK to C_CLK
77+
// always_ff @(posedge c_clk_i)
78+
// if (!c_rst_ni) begin
79+
// tproc_ctrl_rcd <= 0 ;
80+
// tproc_ctrl_r <= 0 ;
81+
// tproc_ctrl_2r <= 0 ;
82+
// tproc_cfg_rcd <= 0 ;
83+
// end else begin
84+
// tproc_ctrl_rcd <= PS_TPROC_CTRL ;
85+
// tproc_ctrl_r <= tproc_ctrl_rcd ;
86+
// tproc_ctrl_2r <= tproc_ctrl_r ;
87+
// tproc_cfg_rcd <= PS_TPROC_CFG ;
88+
// TPROC_CFG <= tproc_cfg_rcd ;
89+
// end
90+
91+
// // The C_TPROC_CTRL is only ONE clock.
92+
// assign TPROC_CTRL = tproc_ctrl_r & ~tproc_ctrl_2r ;
93+
//-------------------------------------------------------
9194

9295
endmodule

firmware/ip/qick_processor/src/qproc_ctrl.sv

Lines changed: 32 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -18,8 +18,6 @@ module qproc_ctrl # (
1818
input wire t_rst_ni ,
1919
input wire c_clk_i ,
2020
input wire c_rst_ni ,
21-
input wire ps_clk_i ,
22-
input wire ps_rst_ni ,
2321
// External Control
2422
input wire proc_start_i ,
2523
input wire proc_stop_i ,
@@ -33,8 +31,10 @@ module qproc_ctrl # (
3331
input wire [3:0] int_time_cmd , //core_usr_operation
3432
input wire [31:0] int_time_dt , //core_usr_operation
3533
// AXI Control
36-
input wire [15:0] xreg_TPROC_CTRL ,
37-
input wire [15:0] xreg_TPROC_CFG ,
34+
input wire [15:0] PS_TPROC_CTRL,
35+
input wire [10:9] PS_TPROC_CFG,
36+
// input wire [15:0] xreg_TPROC_CTRL ,
37+
// input wire [15:0] xreg_TPROC_CFG ,
3838
input wire [31:0] xreg_TPROC_W_DT ,
3939
// QPROC_STATE
4040
input wire all_fifo_full_i ,
@@ -54,6 +54,34 @@ module qproc_ctrl # (
5454
output reg [ 6:0] c_debug_do
5555
);
5656

57+
//-------------------------------------------------------
58+
// Code moved from qproc_axi_reg due to issue #33
59+
logic [15:0] xreg_TPROC_CTRL;
60+
logic [10:9] xreg_TPROC_CFG, TPROC_CFG;
61+
62+
logic [15:0] tproc_ctrl_rcd, tproc_ctrl_r, tproc_ctrl_2r;
63+
logic [10:9] tproc_cfg_rcd;
64+
65+
// From PS_CLK to C_CLK
66+
always_ff @(posedge c_clk_i)
67+
if (!c_rst_ni) begin
68+
tproc_ctrl_rcd <= 0 ;
69+
tproc_ctrl_r <= 0 ;
70+
tproc_ctrl_2r <= 0 ;
71+
tproc_cfg_rcd <= 0 ;
72+
end else begin
73+
tproc_ctrl_rcd <= PS_TPROC_CTRL ;
74+
tproc_ctrl_r <= tproc_ctrl_rcd ;
75+
tproc_ctrl_2r <= tproc_ctrl_r ;
76+
tproc_cfg_rcd <= PS_TPROC_CFG ;
77+
TPROC_CFG <= tproc_cfg_rcd ;
78+
end
79+
80+
// The C_TPROC_CTRL is only ONE clock.
81+
assign xreg_TPROC_CTRL = tproc_ctrl_r & ~tproc_ctrl_2r ;
82+
assign xreg_TPROC_CFG = TPROC_CFG;
83+
//-------------------------------------------------------
84+
5785

5886
// Control
5987
reg t_core_rst_prev_net; // NET Request to RESET the Processor and go to previous state

firmware/ip/qick_processor/xgui/qick_processor_v2_0.tcl

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,8 +3,7 @@ proc init_gui { IPINST } {
33
ipgui::add_param $IPINST -name "Component_Name"
44
#Adding Page
55
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
6-
ipgui::add_static_text $IPINST -name "Version" -parent ${Page_0} -text {Qick_Processor Revision 22 - 2024_10, ( Use Assembler Version v3 rev23 )}
7-
ipgui::add_static_text $IPINST -name "Introduction" -parent ${Page_0} -text {Values for Memory size Port quantity and register amount can be modified in order to make a smaller and Faster processor }
6+
ipgui::add_static_text $IPINST -name "Introduction" -parent ${Page_0} -text {Values for Memory size, port quantity, and register amount can be modified in order to make a smaller and faster processor}
87
#Adding Group
98
set Process [ipgui::add_group $IPINST -name "Process" -parent ${Page_0} -display_name {Processor Options}]
109
set_property tooltip {Process} ${Process}
@@ -44,6 +43,7 @@ proc init_gui { IPINST } {
4443
ipgui::add_param $IPINST -name "OUT_WPORT_QTY" -parent ${GROUP1}
4544
ipgui::add_param $IPINST -name "OUT_DPORT_QTY" -parent ${GROUP1}
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ipgui::add_param $IPINST -name "OUT_DPORT_DW" -parent ${GROUP1}
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ipgui::add_param $IPINST -name "FIFO_DEPTH" -parent ${GROUP1} -widget comboBox
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#Adding Group
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set GROUP [ipgui::add_group $IPINST -name "GROUP" -parent ${OUT_Port_Configuration} -display_name {QICK SIGNALS}]

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