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Merge pull request #143 from openrisc/licence-switch-cern-ohl-v2-w
Licence switch OHDL to CERN OHL-W V2
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‎LICENSE‎

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‎README.md‎

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## License
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This project is licensed under the Open Hardware Description License (OHDL). For
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details please see the [LICENSE](./LICENSE) file or http://juliusbaxter.net/ohdl/
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This project is licensed under the CERN Open Hardware Licence Version 2 - Weakly Reciprocal (CERN-OHL-W). For
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details please see the [LICENSE](./LICENSE) file or https:/cern.ch/cern-ohl
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SPDX-License-Identifier: CERN-OHL-W-2.0
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https://spdx.org/licenses/CERN-OHL-W-2.0.html
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## Configuration
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‎bench/formal/Makefile‎

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###########################################################
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# This Source Code Form is subject to the terms of the
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# Open Hardware Description License, v. 1.0. If a copy
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# of the OHDL was not distributed with this file, You
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# can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
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# SPDX-License-Identifier: CERN-OHL-W-2.0
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#
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# Description: Simplistic makefile for running formal tests
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#

‎bench/formal/f_multiclock_op.v‎

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/* ****************************************************************************
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This Source Code Form is subject to the terms of the
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Open Hardware Description License, v. 1.0. If a copy
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of the OHDL was not distributed with this file, You
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can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
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SPDX-License-Identifier: CERN-OHL-W-2.0
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Description: mor1kx formal multiclock alu operation checker
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‎bench/formal/fspr_master.v‎

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module fspr_master
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/* ****************************************************************************
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SPDX-License-Identifier: CERN-OHL-W-2.0
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***************************************************************************** */
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module fspr_master
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#(
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parameter OPTION_OPERAND_WIDTH = 32
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)

‎bench/formal/fspr_slave.v‎

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/* ****************************************************************************
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SPDX-License-Identifier: CERN-OHL-W-2.0
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***************************************************************************** */
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module fspr_slave
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#(
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parameter OPTION_OPERAND_WIDTH = 32,

‎bench/verilog/mor1kx_monitor.v‎

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/* ****************************************************************************
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This Source Code Form is subject to the terms of the
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Open Hardware Description License, v. 1.0. If a copy
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of the OHDL was not distributed with this file, You
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can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
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SPDX-License-Identifier: CERN-OHL-W-2.0
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Description: mor1kx monitor module
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‎bench/verilog/mor1kx_traceport_monitor.v‎

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/* ****************************************************************************
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SPDX-License-Identifier: CERN-OHL-W-2.0
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***************************************************************************** */
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`include "mor1kx-defines.v"
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`define OR1K_OPCODE_POS 31:26

‎rtl/verilog/mor1kx-defines.v‎

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/* ****************************************************************************
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This Source Code Form is subject to the terms of the
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Open Hardware Description License, v. 1.0. If a copy
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of the OHDL was not distributed with this file, You
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can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
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SPDX-License-Identifier: CERN-OHL-W-2.0
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Description: mor1kx defines
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‎rtl/verilog/mor1kx-sprs.v‎

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/* ****************************************************************************
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This Source Code Form is subject to the terms of the
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Open Hardware Description License, v. 1.0. If a copy
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of the OHDL was not distributed with this file, You
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can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
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SPDX-License-Identifier: CERN-OHL-W-2.0
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Description: SPR definitions
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