Reduce the difference between llvm-head and main branches more more more

Author: khasanovaa

third_party/amd/include/Utils/Utility.h

@@ -6,8 +6,6 @@
 #include <vector>
 namespace mlir::LLVM::AMD {
 
-using llvm::ArrayRef;
-
 template <typename T, typename U, typename BinaryOp>
 std::vector<unsigned> multiDimElementwise(const ArrayRef<T> &lhs,
                                           const ArrayRef<U> &rhs, BinaryOp op) {

third_party/amd/lib/TritonAMDGPUToLLVM/AtomicRMWOpsEmitter.cpp

@@ -405,28 +405,15 @@ Value AtomicRMWEmitter::atomicIntraWaveReduce(RewriterBase &rewriter,
   Value done = b.icmp_eq(chosen, rmwPtr);
   Value mask = targetInfo.ballot(rewriter, loc, i64_ty, done);
   Value start = loopBody->getArgument(0);
-  NamedAttribute noundef = rewriter.getNamedAttr(
-      LLVM::LLVMDialect::getNoUndefAttrName(), rewriter.getUnitAttr());
-  NamedAttribute lowRange = rewriter.getNamedAttr(
-      LLVM::LLVMDialect::getRangeAttrName(),
-      LLVM::ConstantRangeAttr::get(rewriter.getContext(), APInt::getZero(32),
-                                   APInt(32, 32)));
-  NamedAttribute highRange = rewriter.getNamedAttr(
-      LLVM::LLVMDialect::getRangeAttrName(),
-      LLVM::ConstantRangeAttr::get(rewriter.getContext(), APInt::getZero(32),
-                                   APInt(32, 64)));
   Value cnt = b.trunc(i32_ty, generatePopcount64(rewriter, mask));
   Value maskLo = b.trunc(i32_ty, mask);
-  Value mbcntLoRes = ROCDL::MbcntLoOp::create(
-      rewriter, loc, i32_ty, maskLo, b.i32_val(0),
-      /*arg_attrs=*/{}, /*res_attrs=*/
-      rewriter.getArrayAttr(rewriter.getDictionaryAttr({noundef, lowRange})));
+  Value mbcntLoRes =
+      ROCDL::MbcntLoOp::create(rewriter, loc, i32_ty, maskLo, b.i32_val(0),
+                               /*arg_attrs=*/{}, /*res_attrs=*/{});
   Value maskHi = b.trunc(i32_ty, b.lshr(mask, b.i64_val(32)));
-  Value idx = ROCDL::MbcntHiOp::create(
-      rewriter, loc, i32_ty, maskHi, mbcntLoRes,
-      /*arg_attrs=*/{},
-      /*res_attrs=*/
-      rewriter.getArrayAttr(rewriter.getDictionaryAttr({noundef, highRange})));
+  Value idx =
+      ROCDL::MbcntHiOp::create(rewriter, loc, i32_ty, maskHi, mbcntLoRes,
+                               /*arg_attrs=*/{}, /*res_attrs=*/{});
   Value base = b.add(start, cnt);
   Value leader = b.icmp_eq(idx, b.i32_val(0));
   cnt = b.sub(cnt, idx);

third_party/amd/lib/TritonAMDGPUToLLVM/SchedInstructions.cpp

@@ -105,7 +105,7 @@ struct TritonAMDGPULowerInstructionSchedHints
 
   explicit TritonAMDGPULowerInstructionSchedHints(StringRef arch,
                                                   int32_t numStages) {
-    this->arch = arch.str();
+    this->arch = std::move(arch.str());
     this->numStages = numStages;
   }
 
@@ -138,7 +138,7 @@ struct TritonAMDGPUInsertInstructionSchedHints
           TritonAMDGPUInsertInstructionSchedHints> {
 
   explicit TritonAMDGPUInsertInstructionSchedHints(StringRef variant) {
-    this->variant = variant.str();
+    this->variant = std::move(variant.str());
   }
 
   void runOnOperation() override {

third_party/amd/lib/TritonAMDGPUTransforms/CanonicalizePointers.cpp

@@ -1800,7 +1800,7 @@ class ConvertUnimplementedOpUnrealizedCasts
     if (auto integerAttr =
             llvm::dyn_cast_or_null<mlir::IntegerAttr>(maybeAttr)) {
       if (integerAttr.getValue() == 0) {
-        rewriter.RewriterBase::replaceAllUsesWith(castOp.getResult(0), fatPtrBase);
+        rewriter.replaceAllUsesWith(castOp.getResult(0), fatPtrBase);
         rewriter.eraseOp(castOp);
         return success();
       }
@@ -1810,7 +1810,7 @@ class ConvertUnimplementedOpUnrealizedCasts
         fatPtrs.at({fatPtrBase, fatPtrOffset});
     auto newPtr = createTensorPointer(rewriter, fatPtrBase, fatPtrOffset,
                                       castOp.getLoc(), fatPtrAttrs);
-    rewriter.RewriterBase::replaceAllUsesWith(newPtr, fatPtrBase);
+    rewriter.replaceAllUsesWith(newPtr, fatPtrBase);
     rewriter.eraseOp(castOp);
     return success();
   }