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BL2 Built : 14:02:05, Nov 23 2020. g12a g966c864 - gongwei.chen@droid11-sz
Board ID = 7
Set cpu clk to 24M
Set clk81 to 24M
CPU clk: 1200 MHz
Set clk81 to 166.6M
eMMC boot @ 0
sw8 s
board id: 7
Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
fw parse done
PIEI prepare done
00000000
emmc switch 1 ok
ddr saved addr:00016000
Load ddr parameter from eMMC, src: 0x02c00000, des: 0xfffd0000, size: 0x00001000, part: 0
00000000
emmc switch 0 ok
fastboot data verify
result: 255
Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
LPDDR4 probe
LPDDR4_PHY_V_0_1_22-Built : 15:59:30, May 25 2020. g12a gb6bfa83 - gongwei.chen@droid11-sz
ddr clk to 1176MHz
dmc_version 0000
Check phy result
INFO : End of CA training
INFO : End of initialization
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : End of read dq deskew training
INFO : End of MPR read delay center optimization
INFO : End of Write leveling coarse delay
INFO : End of read delay center optimization
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of MPR read delay center optimization
INFO : End of write delay center optimization
INFO : End of read delay center optimization
INFO : End of max read latency training
INFO : Training has run successfully!
1D training succeed
Check phy result
INFO : End of initialization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : Training has run successfully!
BL2 Built : 14:02:05, Nov 23 2020. g12a g966c864 - gongwei.chen@droid11-sz
Board ID = 7
Set cpu clk to 24M
Set clk81 to 24M
CPU clk: 1200 MHz
Set clk81 to 166.6M
eMMC boot @ 0
sw8 s
board id: 7
Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
fw parse done
PIEI prepare done
00000000
emmc switch 1 ok
ddr saved addr:00016000
Load ddr parameter from eMMC, src: 0x02c00000, des: 0xfffd0000, size: 0x00001000, part: 0
00000000
emmc switch 0 ok
fastboot data verify
result: 255
Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
LPDDR4 probe
LPDDR4_PHY_V_0_1_22-Built : 15:59:30, May 25 2020. g12a gb6bfa83 - gongwei.chen@droid11-sz
ddr clk to 1176MHz
dmc_version 0000
Check phy result
INFO : End of CA training
INFO : End of initialization
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : End of read dq deskew training
INFO : End of MPR read delay center optimization
INFO : End of Write leveling coarse delay
INFO : End of read delay center optimization
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of MPR read delay center optimization
INFO : End of write delay center optimization
INFO : End of read delay center optimization
INFO : End of max read latency training
INFO : Training has run successfully!
1D training succeed
Check phy result
INFO : End of initialization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : Training has run successfully!
Usage:
irkey - No additional help available.
time_out = 0
key[0] = 3ec14cb3
key[1] = 3ec1fd01
key[2] = 3ec1dd22
irkey - irkey ... - maximum value of N: 10
Usage:
irkey - No additional help available.
Command: bcb uboot-command
Start read misc partition datas!
BCB hasn't any datas,exit!
InUsbBurn
wait for phy ready count is 0
noSof
sof timeout, reset usb phy tuning
card out
[MSG]mmcinfo failed!
card out
(Re)start USB...
USB0: USB3.0 XHCI init start
Register 3000140 NbrPorts 2
Starting the controller
USB XHCI 1.10
scanning bus 0 for devices... 2 USB Device(s) found
scanning usb for storage devices... init_part() 282: PART_TYPE_DOS
1 Storage Device(s) found
reading aml_autoscript
709 bytes read in 28 ms (24.4 KiB/s)
Executing script at 01080000
Error: "bootfromsd" not defined
Saving Environment to aml-storage...
mmc env offset: 0x6c00000
Writing to MMC(1)... done
reboot use default mode: normal
bl31 reboot reason: 0xd
bl31 reboot reason: 0x1
system cmd 1.
G12A:BL:0253b8:61aa2d;FEAT:E0F83180:2000;POC:F;RCY:0;EMMC:0;READ:0;0.0;
bl2_stage_init 0x01
bl2_stage_init 0x81
hw id: 0x0000 - pwm id 0x01
bl2_stage_init 0xc1
bl2_stage_init 0x02
BL2 Built : 14:02:05, Nov 23 2020. g12a g966c864 - gongwei.chen@droid11-sz
Board ID = 7
Set cpu clk to 24M
Set clk81 to 24M
CPU clk: 1200 MHz
Set clk81 to 166.6M
eMMC boot @ 0
sw8 s
board id: 7
Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
fw parse done
PIEI prepare done
00000000
emmc switch 1 ok
ddr saved addr:00016000
Load ddr parameter from eMMC, src: 0x02c00000, des: 0xfffd0000, size: 0x00001000, part: 0
00000000
emmc switch 0 ok
fastboot data verify
result: 255
Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
LPDDR4 probe
LPDDR4_PHY_V_0_1_22-Built : 15:59:30, May 25 2020. g12a gb6bfa83 - gongwei.chen@droid11-sz
ddr clk to 1176MHz
dmc_version 0000
Check phy result
INFO : End of CA training
INFO : End of initialization
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : End of read dq deskew training
INFO : End of MPR read delay center optimization
INFO : End of Write leveling coarse delay
INFO : End of read delay center optimization
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of MPR read delay center optimization
INFO : End of write delay center optimization
INFO : End of read delay center optimization
INFO : End of max read latency training
INFO : Training has run successfully!
1D training succeed
Check phy result
INFO : End of initialization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : Training has run successfully!
Usage:
irkey - No additional help available.
time_out = 0
key[0] = 3ec14cb3
key[1] = 3ec1fd01
key[2] = 3ec1dd22
irkey - irkey ... - maximum value of N: 10
Usage:
irkey - No additional help available.
Command: bcb uboot-command
Start read misc partition datas!
BCB hasn't any datas,exit!
rebootmode=normal
Saving Environment to aml-storage...
mmc env offset: 0x6c00000
Writing to MMC(1)... done
Hit Enter or space or Ctrl+C key to stop autoboot -- : 0
card out
(Re)start USB...
USB0: USB3.0 XHCI init start
Register 3000140 NbrPorts 2
Starting the controller
USB XHCI 1.10
scanning bus 0 for devices... 2 USB Device(s) found
scanning usb for storage devices... init_part() 282: PART_TYPE_DOS
1 Storage Device(s) found
reading s905_autoscript
1654 bytes read in 54 ms (29.3 KiB/s)
Executing script at 01020000
start amlogic old u-boot
Error: "bootfromsd" not defined
card out
** Bad device mmc 0 **
reading boot_android
** Unable to read file boot_android **
card out
** Bad device mmc 0 **
reading u-boot.ext
** Unable to read file u-boot.ext **
card out
** Bad device mmc 0 **
start test usb
reading uEnv.txt
327 bytes read in 43 ms (6.8 KiB/s)
mac=A0:4C:0C:04:AD:1F
reading /zImage
27298304 bytes read in 1250 ms (20.8 MiB/s)
reading /uInitrd
17983027 bytes read in 869 ms (19.7 MiB/s)
reading /dtb/amlogic/meson-g12a-s905l3a-e900v22c.dtb
73357 bytes read in 234 ms (305.7 KiB/s)
Error: "aadmac" not defined
libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND
[rsvmem] fdt get prop fail.
Loading init Ramdisk from Legacy Image at 13000000 ...
Image Name: uInitrd
Image Type: AArch64 Linux RAMDisk Image (gzip compressed)
Data Size: 17982963 Bytes = 17.1 MiB
Load Address: 00000000
Entry Point: 00000000
Verifying Checksum ... OK
[store]Is good fdt check header, no need decrypt!
active_slot is normal
load dtb from 0x1000000 ......
Amlogic multi-dtb tool
Single dtb detected
Flattened Device Tree blob at 01000000
Booting using the fdt blob at 0x1000000
find 1 dtbos
No androidboot.dtbo_idx configured
And no dtbos will be applied
libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND
[rsvmem] fdt get prop fail.
Loading Ramdisk to 32d0c000, end 33e325f3 ... OK
Loading Device Tree to 000000001ffeb000, end 000000001fffff42 ... OK
fdt_fixup_memory_banks, reg:000000001fff69d4
DTS already have 'reg' property
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系统是Armbian_23.05.0_amlogic_s905l3a_bullseye_5.15.107_server_ U盘一直无法启动 有没有哪位大神能帮忙分析分析下原因,谢谢!
G12A:BL:0253b8:61aa2d;FEAT:E0F83180:2000;POC:F;RCY:0;EMMC:0;READ:0;0.0;
bl2_stage_init 0x01
bl2_stage_init 0x81
hw id: 0x0000 - pwm id 0x01
bl2_stage_init 0xc1
bl2_stage_init 0x02
L0:00000000
L1:00000703
L2:00008267
L3:04000000
S1:00000000
B2:00002000
B1:e0f83180
TE: 161848
BL2 Built : 14:02:05, Nov 23 2020. g12a g966c864 - gongwei.chen@droid11-sz
Board ID = 7
Set cpu clk to 24M
Set clk81 to 24M
CPU clk: 1200 MHz
Set clk81 to 166.6M
eMMC boot @ 0
sw8 s
board id: 7
Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
fw parse done
PIEI prepare done
00000000
emmc switch 1 ok
ddr saved addr:00016000
Load ddr parameter from eMMC, src: 0x02c00000, des: 0xfffd0000, size: 0x00001000, part: 0
00000000
emmc switch 0 ok
fastboot data verify
result: 255
Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
LPDDR4 probe
LPDDR4_PHY_V_0_1_22-Built : 15:59:30, May 25 2020. g12a gb6bfa83 - gongwei.chen@droid11-sz
ddr clk to 1176MHz
dmc_version 0000
Check phy result
INFO : End of CA training
INFO : End of initialization
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : End of read dq deskew training
INFO : End of MPR read delay center optimization
INFO : End of Write leveling coarse delay
INFO : End of read delay center optimization
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of MPR read delay center optimization
INFO : End of write delay center optimization
INFO : End of read delay center optimization
INFO : End of max read latency training
INFO : Training has run successfully!
1D training succeed
Check phy result
INFO : End of initialization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : Training has run successfully!
soc_vref_reg_value 0x 00000024 00000024 00000022 00000023 00000022 00000021 00000022 00000022 00000023 00000023 00000022 00000024 00000022 00000023 0000001f 00000021 00000021 00000023 00000022 00000022 00000023 0000001f 00000021 00000022 00000022 00000024 00000022 00000021 00000021 00000023 00000020 00000022 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
dram_vref_reg_value 0x 0000005f
2D training succeed
auto size-- 65535DDR cs0 size: 1024MB
DDR cs1 size: 0MB
DMC_DDR_CTRL: 00c0002bDDR size: 1024MB
cs0 DataBus test pass
cs0 AddrBus test pass
non-sec scramble use zero key
ddr scramble enabled
100bdlr_step_size ps== 429
result report
boot times 0Enable ddr reg access
00000000
emmc switch 3 ok
Authentication key not yet programmed
get rpmb counter error 0x00000007
00000000
emmc switch 0 ok
Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x000d6a00, part: 0
0.0;M3 CHK:0;cm4_sp_mode 0
[Image: g12a_v1.1.3394-7d43064d5 2020-05-07 15:37:06 gongwei.chen@droid11-sz]
OPS=0x70
ring efuse init
28 0c 70 00 01 1d 05 00 00 10 31 34 33 52 4d 50
[0.014270 Inits done]
secure task start!
high task start!
low task start!
boot bl31
NOTICE: BL31: v1.3(release):9d705ef56-dirty
NOTICE: BL31: Built : 19:18:02, Jul 28 2021
NOTICE: BL31: G12A normal boot!
NOTICE: BL31: BL33 decompress pass
ERROR: Error initializing runtime service opteed_fast
U-Boot 2015.01 (Sep 26 2021 - 14:35:31)
DRAM: 1 GiB
Relocation Offset is: 36e45000
mmu cfg end: 0x40000000
mmu cfg end: 0x40000000
spi_post_bind(spifc): req_seq = 0
register usb cfg[0][1] = 0000000037f3be68
gpio: pin GPIOAO_9 (gpio 9) value is 0
NAND: get_sys_clk_rate_mtd() 292, clock setting 200!
bus cycle0: 6,timing: 7
NAND device id: 0 ff ff ff ff ff
No NAND device found!!!
nand init failed: -6
get_sys_clk_rate_mtd() 292, clock setting 200!
bus cycle0: 6,timing: 7
NAND device id: 0 ff ff ff ff ff
No NAND device found!!!
nand init failed: -6
MMC: aml_priv->desc_buf = 0x0000000033e35d90
aml_priv->desc_buf = 0x0000000033e380d0
SDIO Port B: 0, SDIO Port C: 1
co-phase 0x2, tx-dly 0, clock 400000
co-phase 0x2, tx-dly 0, clock 400000
co-phase 0x2, tx-dly 0, clock 400000
emmc/sd response timeout, cmd8, cmd->cmdarg=0x1aa, status=0x1ff2800
emmc/sd response timeout, cmd55, cmd->cmdarg=0x0, status=0x1ff2800
co-phase 0x2, tx-dly 0, clock 400000
co-phase 0x2, tx-dly 0, clock 40000000
[set_emmc_calc_fixed_adj][875]find fixed adj_delay=20
init_part() 297: PART_TYPE_AML
[mmc_init] mmc init success
Amlogic multi-dtb tool
GZIP format, decompress...
Multi dtb detected
Multi dtb tool version: v2 .
Support 3 dtbs.
aml_dt soc: g12a platform: u212 variant: 1g
dtb 0 soc: g12a plat: u212 vari: 1g
dtb 1 soc: g12a plat: u212 vari: 2g
dtb 2 soc: sm1 plat: ac213 vari: 2g
Find match dtb: 0
start dts,buffer=0000000033e3a920,dt_addr=0000000033e3a920
get_partition_from_dts() 92: ret 0
Amlogic multi-dtb tool
Single dtb detected
parts: 21
00: logo 0000000000800000 1
01: recovery 0000000001800000 1
02: misc 0000000000800000 1
03: dtbo 0000000000800000 1
04: cri_data 0000000000800000 2
05: param 0000000001000000 2
06: boot 0000000001000000 1
set has_boot_slot = 0
07: rsv 0000000001000000 1
08: metadata 0000000001000000 1
09: vbmeta 0000000000200000 1
10: tee 0000000002000000 1
11: vendor 0000000014000000 1
12: skmac 0000000000400000 1
13: odm 0000000001000000 1
14: system 0000000050000000 1
15: product 0000000008000000 1
16: ctc 0000000010000000 1
17: skparam 0000000001000000 2
18: skbackup 0000000030000000 2
19: cache 0000000040000000 2
20: data ffffffffffffffff 4
init_part() 297: PART_TYPE_AML
eMMC/TSD partition table have been checked OK!
crc32_s:0x1577dad == storage crc_pattern:0x1577dad!!!
crc32_s:0xee152b83 == storage crc_pattern:0xee152b83!!!
crc32_s:0x79f50f07 == storage crc_pattern:0x79f50f07!!!
mmc env offset: 0x6c00000
In: serial
Out: serial
Err: serial
reboot_mode=cold_boot
[store]To run cmd[emmc dtb_read 0x1000000 0x40000]
_verify_dtb_checksum()-3476: calc 8fee3e9b, store 8fee3e9b
_verify_dtb_checksum()-3476: calc 8fee3e9b, store 8fee3e9b
dtb_read()-3691: total valid 2
update_old_dtb()-3672: do nothing
Amlogic multi-dtb tool
GZIP format, decompress...
Multi dtb detected
Multi dtb tool version: v2 .
Support 3 dtbs.
aml_dt soc: g12a platform: u212 variant: 1g
dtb 0 soc: g12a plat: u212 vari: 1g
dtb 1 soc: g12a plat: u212 vari: 2g
dtb 2 soc: sm1 plat: ac213 vari: 2g
Find match dtb: 0
amlkey_init() enter!
[EFUSE_MSG]keynum is 4
vpu: driver version: v20190313
vpu: detect chip type: 8
vpu: clk_level default: 7(666667000Hz), max: 7(666667000Hz)
vpu: clk_level in dts: 7
vpu: vpu_power_on
vpu: set_vpu_clk
vpu: set clk: 666667000Hz, readback: 666666667Hz(0x100)
vpu: set_vpu_clk finish
vpu: vpu_module_init_config
vpp: vpp_init
vpp: vpp osd2 matrix rgb2yuv..............
hdr_func 4, hdr_process_select 0x1
cvbs: cpuid:0x28
vdac_gsw_init: 0x0
cvbs: find performance_pal config
aml_config_dtb 637
aml_config_dtb 667
co_phase = <0x00000003>
caps2 = "MMC_CAP2_HS200"
f_max = <0x02faf080>
status = "disabled"
status = "okay"
wipe_data=successful
wipe_cache=successful
upgrade_step=2
reboot_mode:::: cold_boot
ext4logoLoadCmd=ext4load mmc 1:${logoPart} ${logoLoadAddr} ${ext4LogoPath}
6220854 bytes read in 179 ms (33.1 MiB/s)
[imgread]load bmp from ext4 part okay
bmp pixel: 24
[OSD]load fb addr from dts:/meson-fb
[OSD]set initrd_high: 0x3f800000
[OSD]fb_addr for logo: 0x3f800000
[OSD]load fb addr from dts:/meson-fb
[OSD]fb_addr for logo: 0x3f800000
[OSD]VPP_OFIFO_SIZE:0xfff01fff
[CANVAS]canvas init
[CANVAS]addr=0x3f800000 width=5760, height=2160
[OSD]osd_hw.free_dst_data: 0,719,0,479
[OSD]osd1_update_disp_freescale_enable
cvbs: outputmode[480p60hz] is invalid
vpp: vpp_matrix_update: 2
set hdmitx VIC = 3
aml_audio_init
config HPLL = 4324320 frac_rate = 0
HPLL: 0x3b0004b4
HPLL: 0x1b0004b4
HPLL: 0xdb0004b4
config HPLL done
j = 1 vid_clk_div = 1
hdmitx: set enc for VIC: 3
hdmitx phy setting done
rx version is 1.4 or below div=10
hdmtix: set audio
hdmi_tx_set: save mode: 480p60hz, attr: rgb,8bit, hdmichecksum:
Saving Environment to aml-storage...
mmc env offset: 0x6c00000
Writing to MMC(1)... done
hdr_packet
vpp: hdr_policy = 2
vpp: Rx hdr_info.hdr_sup_eotf_smpte_st_2084 = 0
time_out = 493e0
key[0] = 66994cb3
key[1] = 6699fd01
key[2] = 6699dd22
irkey - irkey ... - maximum value of N: 10
Usage:
irkey - No additional help available.
time_out = 0
key[0] = 3ec14cb3
key[1] = 3ec1fd01
key[2] = 3ec1dd22
irkey - irkey ... - maximum value of N: 10
Usage:
irkey - No additional help available.
Command: bcb uboot-command
Start read misc partition datas!
BCB hasn't any datas,exit!
InUsbBurn
wait for phy ready count is 0
noSof
sof timeout, reset usb phy tuning
rebootmode=cold_boot
Saving Environment to aml-storage...
mmc env offset: 0x6c00000
Writing to MMC(1)... done
Hit Enter or space or Ctrl+C key to stop autoboot -- : 0
g12a_u212_v1#
g12a_u212_v1#
g12a_u212_v1#
g12a_u212_v1#
g12a_u212_v1#
g12a_u212_v1#
g12a_u212_v1#
g12a_u212_v1#
g12a_u212_v1#
g12a_u212_v1#
g12a_u212_v1#
g12a_u212_v1#
g12a_u212_v1#
g12a_u212_v1#
g12a_u212_v1#
g12a_u212_v1#
g12a_u212_v1#
g12a_u212_v1#
g12a_u212_v1#
g12a_u212_v1#reboot update
reboot mode: update
bl31 reboot reason: 0xd
bl31 reboot reason: 0x3
system cmd 1.
G12A:BL:0253b8:61aa2d;FEAT:E0F83180:2000;POC:F;RCY:0;EMMC:0;READ:0;0.0;
bl2_stage_init 0x01
bl2_stage_init 0x81
hw id: 0x0000 - pwm id 0x01
bl2_stage_init 0xc1
bl2_stage_init 0x02
L0:00000000
L1:00000703
L2:00008267
L3:04000000
S1:00000000
B2:00002000
B1:e0f83180
TE: 159882
BL2 Built : 14:02:05, Nov 23 2020. g12a g966c864 - gongwei.chen@droid11-sz
Board ID = 7
Set cpu clk to 24M
Set clk81 to 24M
CPU clk: 1200 MHz
Set clk81 to 166.6M
eMMC boot @ 0
sw8 s
board id: 7
Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
fw parse done
PIEI prepare done
00000000
emmc switch 1 ok
ddr saved addr:00016000
Load ddr parameter from eMMC, src: 0x02c00000, des: 0xfffd0000, size: 0x00001000, part: 0
00000000
emmc switch 0 ok
fastboot data verify
result: 255
Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
LPDDR4 probe
LPDDR4_PHY_V_0_1_22-Built : 15:59:30, May 25 2020. g12a gb6bfa83 - gongwei.chen@droid11-sz
ddr clk to 1176MHz
dmc_version 0000
Check phy result
INFO : End of CA training
INFO : End of initialization
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : End of read dq deskew training
INFO : End of MPR read delay center optimization
INFO : End of Write leveling coarse delay
INFO : End of read delay center optimization
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of MPR read delay center optimization
INFO : End of write delay center optimization
INFO : End of read delay center optimization
INFO : End of max read latency training
INFO : Training has run successfully!
1D training succeed
Check phy result
INFO : End of initialization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : Training has run successfully!
soc_vref_reg_value 0x 00000024 00000024 00000022 00000023 00000022 00000021 00000022 00000022 00000023 00000023 00000022 00000025 00000022 00000023 0000001f 00000021 00000022 00000023 00000022 00000023 00000023 0000001f 00000021 00000021 00000022 00000024 00000022 00000021 00000021 00000023 00000020 00000022 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
dram_vref_reg_value 0x 0000005f
2D training succeed
auto size-- 65535DDR cs0 size: 1024MB
DDR cs1 size: 0MB
DMC_DDR_CTRL: 00c0002bDDR size: 1024MB
cs0 DataBus test pass
cs0 AddrBus test pass
non-sec scramble use zero key
ddr scramble enabled
100bdlr_step_size ps== 438
result report
boot times 1Enable ddr reg access
00000000
emmc switch 3 ok
Authentication key not yet programmed
get rpmb counter error 0x00000007
00000000
emmc switch 0 ok
Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x000d6a00, part: 0
0.0;M3 CHK:0;cm4_sp_mode 0
[Image: g12a_v1.1.3394-7d43064d5 2020-05-07 15:37:06 gongwei.chen@droid11-sz]
OPS=0x70
ring efuse init
28 0c 70 00 01 1d 05 00 00 10 31 34 33 52 4d 50
[0.858008 Inits done]
secure task start!
high task start!
low task start!
boot bl31
NOTICE: BL31: v1.3(release):9d705ef56-dirty
NOTICE: BL31: Built : 19:18:02, Jul 28 2021
NOTICE: BL31: G12A normal boot!
NOTICE: BL31: BL33 decompress pass
ERROR: Error initializing runtime service opteed_fast
U-Boot 2015.01 (Sep 26 2021 - 14:35:31)
DRAM: 1 GiB
Relocation Offset is: 36e45000
mmu cfg end: 0x40000000
mmu cfg end: 0x40000000
spi_post_bind(spifc): req_seq = 0
register usb cfg[0][1] = 0000000037f3be68
gpio: pin GPIOAO_9 (gpio 9) value is 0
NAND: get_sys_clk_rate_mtd() 292, clock setting 200!
bus cycle0: 6,timing: 7
NAND device id: 0 ff ff ff ff ff
No NAND device found!!!
nand init failed: -6
get_sys_clk_rate_mtd() 292, clock setting 200!
bus cycle0: 6,timing: 7
NAND device id: 0 ff ff ff ff ff
No NAND device found!!!
nand init failed: -6
MMC: aml_priv->desc_buf = 0x0000000033e35d90
aml_priv->desc_buf = 0x0000000033e380d0
SDIO Port B: 0, SDIO Port C: 1
co-phase 0x2, tx-dly 0, clock 400000
co-phase 0x2, tx-dly 0, clock 400000
co-phase 0x2, tx-dly 0, clock 400000
emmc/sd response timeout, cmd8, cmd->cmdarg=0x1aa, status=0x1ff2800
emmc/sd response timeout, cmd55, cmd->cmdarg=0x0, status=0x1ff2800
co-phase 0x2, tx-dly 0, clock 400000
co-phase 0x2, tx-dly 0, clock 40000000
[set_emmc_calc_fixed_adj][875]find fixed adj_delay=20
init_part() 297: PART_TYPE_AML
[mmc_init] mmc init success
Amlogic multi-dtb tool
GZIP format, decompress...
Multi dtb detected
Multi dtb tool version: v2 .
Support 3 dtbs.
aml_dt soc: g12a platform: u212 variant: 1g
dtb 0 soc: g12a plat: u212 vari: 1g
dtb 1 soc: g12a plat: u212 vari: 2g
dtb 2 soc: sm1 plat: ac213 vari: 2g
Find match dtb: 0
start dts,buffer=0000000033e3a920,dt_addr=0000000033e3a920
get_partition_from_dts() 92: ret 0
Amlogic multi-dtb tool
Single dtb detected
parts: 21
00: logo 0000000000800000 1
01: recovery 0000000001800000 1
02: misc 0000000000800000 1
03: dtbo 0000000000800000 1
04: cri_data 0000000000800000 2
05: param 0000000001000000 2
06: boot 0000000001000000 1
set has_boot_slot = 0
07: rsv 0000000001000000 1
08: metadata 0000000001000000 1
09: vbmeta 0000000000200000 1
10: tee 0000000002000000 1
11: vendor 0000000014000000 1
12: skmac 0000000000400000 1
13: odm 0000000001000000 1
14: system 0000000050000000 1
15: product 0000000008000000 1
16: ctc 0000000010000000 1
17: skparam 0000000001000000 2
18: skbackup 0000000030000000 2
19: cache 0000000040000000 2
20: data ffffffffffffffff 4
init_part() 297: PART_TYPE_AML
eMMC/TSD partition table have been checked OK!
crc32_s:0x1577dad == storage crc_pattern:0x1577dad!!!
crc32_s:0xee152b83 == storage crc_pattern:0xee152b83!!!
crc32_s:0x79f50f07 == storage crc_pattern:0x79f50f07!!!
mmc env offset: 0x6c00000
In: serial
Out: serial
Err: serial
reboot_mode=update
[store]To run cmd[emmc dtb_read 0x1000000 0x40000]
_verify_dtb_checksum()-3476: calc 8fee3e9b, store 8fee3e9b
_verify_dtb_checksum()-3476: calc 8fee3e9b, store 8fee3e9b
dtb_read()-3691: total valid 2
update_old_dtb()-3672: do nothing
Amlogic multi-dtb tool
GZIP format, decompress...
Multi dtb detected
Multi dtb tool version: v2 .
Support 3 dtbs.
aml_dt soc: g12a platform: u212 variant: 1g
dtb 0 soc: g12a plat: u212 vari: 1g
dtb 1 soc: g12a plat: u212 vari: 2g
dtb 2 soc: sm1 plat: ac213 vari: 2g
Find match dtb: 0
amlkey_init() enter!
[EFUSE_MSG]keynum is 4
vpu: driver version: v20190313
vpu: detect chip type: 8
vpu: clk_level default: 7(666667000Hz), max: 7(666667000Hz)
vpu: clk_level in dts: 7
vpu: vpu_power_on
vpu: set_vpu_clk
vpu: set clk: 666667000Hz, readback: 666666667Hz(0x100)
vpu: set_vpu_clk finish
vpu: vpu_module_init_config
vpp: vpp_init
vpp: vpp osd2 matrix rgb2yuv..............
hdr_func 4, hdr_process_select 0x1
cvbs: cpuid:0x28
vdac_gsw_init: 0x0
cvbs: find performance_pal config
aml_config_dtb 637
aml_config_dtb 667
co_phase = <0x00000003>
caps2 = "MMC_CAP2_HS200"
f_max = <0x02faf080>
status = "disabled"
status = "okay"
wipe_data=successful
wipe_cache=successful
upgrade_step=2
reboot_mode:::: update
ext4logoLoadCmd=ext4load mmc 1:${logoPart} ${logoLoadAddr} ${ext4LogoPath}
6220854 bytes read in 178 ms (33.3 MiB/s)
[imgread]load bmp from ext4 part okay
bmp pixel: 24
[OSD]load fb addr from dts:/meson-fb
[OSD]set initrd_high: 0x3f800000
[OSD]fb_addr for logo: 0x3f800000
[OSD]load fb addr from dts:/meson-fb
[OSD]fb_addr for logo: 0x3f800000
[OSD]VPP_OFIFO_SIZE:0xfff01fff
[CANVAS]canvas init
[CANVAS]addr=0x3f800000 width=5760, height=2160
[OSD]osd_hw.free_dst_data: 0,719,0,479
[OSD]osd1_update_disp_freescale_enable
cvbs: outputmode[480p60hz] is invalid
vpp: vpp_matrix_update: 2
set hdmitx VIC = 3
aml_audio_init
config HPLL = 4324320 frac_rate = 0
HPLL: 0x3b0004b4
HPLL: 0x1b0004b4
HPLL: 0xdb0004b4
config HPLL done
j = 1 vid_clk_div = 1
hdmitx: set enc for VIC: 3
hdmitx phy setting done
rx version is 1.4 or below div=10
hdmtix: set audio
hdmi_tx_set: save mode: 480p60hz, attr: rgb,8bit, hdmichecksum:
Saving Environment to aml-storage...
mmc env offset: 0x6c00000
Writing to MMC(1)... done
hdr_packet
vpp: hdr_policy = 2
vpp: Rx hdr_info.hdr_sup_eotf_smpte_st_2084 = 0
time_out = 493e0
key[0] = 66994cb3
key[1] = 6699fd01
key[2] = 6699dd22
irkey - irkey ... - maximum value of N: 10
Usage:
irkey - No additional help available.
time_out = 0
key[0] = 3ec14cb3
key[1] = 3ec1fd01
key[2] = 3ec1dd22
irkey - irkey ... - maximum value of N: 10
Usage:
irkey - No additional help available.
Command: bcb uboot-command
Start read misc partition datas!
BCB hasn't any datas,exit!
InUsbBurn
wait for phy ready count is 0
noSof
sof timeout, reset usb phy tuning
card out
[MSG]mmcinfo failed!
card out
(Re)start USB...
USB0: USB3.0 XHCI init start
Register 3000140 NbrPorts 2
Starting the controller
USB XHCI 1.10
scanning bus 0 for devices... 2 USB Device(s) found
scanning usb for storage devices... init_part() 282: PART_TYPE_DOS
1 Storage Device(s) found
reading aml_autoscript
709 bytes read in 28 ms (24.4 KiB/s)
Executing script at 01080000
Error: "bootfromsd" not defined
Saving Environment to aml-storage...
mmc env offset: 0x6c00000
Writing to MMC(1)... done
reboot use default mode: normal
bl31 reboot reason: 0xd
bl31 reboot reason: 0x1
system cmd 1.
G12A:BL:0253b8:61aa2d;FEAT:E0F83180:2000;POC:F;RCY:0;EMMC:0;READ:0;0.0;
bl2_stage_init 0x01
bl2_stage_init 0x81
hw id: 0x0000 - pwm id 0x01
bl2_stage_init 0xc1
bl2_stage_init 0x02
L0:00000000
L1:00000703
L2:00008267
L3:04000000
S1:00000000
B2:00002000
B1:e0f83180
TE: 159898
BL2 Built : 14:02:05, Nov 23 2020. g12a g966c864 - gongwei.chen@droid11-sz
Board ID = 7
Set cpu clk to 24M
Set clk81 to 24M
CPU clk: 1200 MHz
Set clk81 to 166.6M
eMMC boot @ 0
sw8 s
board id: 7
Load FIP HDR DDR from eMMC, src: 0x00010200, des: 0xfffd0000, size: 0x00004000, part: 0
fw parse done
PIEI prepare done
00000000
emmc switch 1 ok
ddr saved addr:00016000
Load ddr parameter from eMMC, src: 0x02c00000, des: 0xfffd0000, size: 0x00001000, part: 0
00000000
emmc switch 0 ok
fastboot data verify
result: 255
Cfg max: 12, cur: 1. Board id: 255. Force loop cfg
LPDDR4 probe
LPDDR4_PHY_V_0_1_22-Built : 15:59:30, May 25 2020. g12a gb6bfa83 - gongwei.chen@droid11-sz
ddr clk to 1176MHz
dmc_version 0000
Check phy result
INFO : End of CA training
INFO : End of initialization
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of read enable training
INFO : End of fine write leveling
INFO : End of read dq deskew training
INFO : End of MPR read delay center optimization
INFO : End of Write leveling coarse delay
INFO : End of read delay center optimization
INFO : Training has run successfully!
Check phy result
INFO : End of initialization
INFO : End of MPR read delay center optimization
INFO : End of write delay center optimization
INFO : End of read delay center optimization
INFO : End of max read latency training
INFO : Training has run successfully!
1D training succeed
Check phy result
INFO : End of initialization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D read delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : End of 2D write delay Voltage center optimization
INFO : Training has run successfully!
soc_vref_reg_value 0x 00000023 00000024 00000021 00000022 00000022 00000021 00000022 00000022 00000023 00000023 00000021 00000024 00000022 00000023 0000001f 00000021 00000021 00000023 00000022 00000022 00000023 0000001f 00000021 00000021 00000022 00000024 00000022 00000021 00000021 00000023 00000020 00000022 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
dram_vref_reg_value 0x 0000005e
2D training succeed
auto size-- 65535DDR cs0 size: 1024MB
DDR cs1 size: 0MB
DMC_DDR_CTRL: 00c0002bDDR size: 1024MB
cs0 DataBus test pass
cs0 AddrBus test pass
non-sec scramble use zero key
ddr scramble enabled
100bdlr_step_size ps== 429
result report
boot times 2Enable ddr reg access
00000000
emmc switch 3 ok
Authentication key not yet programmed
get rpmb counter error 0x00000007
00000000
emmc switch 0 ok
Load FIP HDR from eMMC, src: 0x00010200, des: 0x01700000, size: 0x00004000, part: 0
Load BL3X from eMMC, src: 0x00078200, des: 0x01768000, size: 0x000d6a00, part: 0
0.0;M3 CHK:0;cm4_sp_mode 0
[Image: g12a_v1.1.3394-7d43064d5 2020-05-07 15:37:06 gongwei.chen@droid11-sz]
OPS=0x70
ring efuse init
28 0c 70 00 01 1d 05 00 00 10 31 34 33 52 4d 50
[0.858017 Inits done]
secure task start!
high task start!
low task start!
boot bl31
NOTICE: BL31: v1.3(release):9d705ef56-dirty
NOTICE: BL31: Built : 19:18:02, Jul 28 2021
NOTICE: BL31: G12A normal boot!
NOTICE: BL31: BL33 decompress pass
ERROR: Error initializing runtime service opteed_fast
U-Boot 2015.01 (Sep 26 2021 - 14:35:31)
DRAM: 1 GiB
Relocation Offset is: 36e45000
mmu cfg end: 0x40000000
mmu cfg end: 0x40000000
spi_post_bind(spifc): req_seq = 0
register usb cfg[0][1] = 0000000037f3be68
gpio: pin GPIOAO_9 (gpio 9) value is 0
NAND: get_sys_clk_rate_mtd() 292, clock setting 200!
bus cycle0: 6,timing: 7
NAND device id: 0 ff ff ff ff ff
No NAND device found!!!
nand init failed: -6
get_sys_clk_rate_mtd() 292, clock setting 200!
bus cycle0: 6,timing: 7
NAND device id: 0 ff ff ff ff ff
No NAND device found!!!
nand init failed: -6
MMC: aml_priv->desc_buf = 0x0000000033e35d90
aml_priv->desc_buf = 0x0000000033e380d0
SDIO Port B: 0, SDIO Port C: 1
co-phase 0x2, tx-dly 0, clock 400000
co-phase 0x2, tx-dly 0, clock 400000
co-phase 0x2, tx-dly 0, clock 400000
emmc/sd response timeout, cmd8, cmd->cmdarg=0x1aa, status=0x1ff2800
emmc/sd response timeout, cmd55, cmd->cmdarg=0x0, status=0x1ff2800
co-phase 0x2, tx-dly 0, clock 400000
co-phase 0x2, tx-dly 0, clock 40000000
[set_emmc_calc_fixed_adj][875]find fixed adj_delay=20
init_part() 297: PART_TYPE_AML
[mmc_init] mmc init success
Amlogic multi-dtb tool
GZIP format, decompress...
Multi dtb detected
Multi dtb tool version: v2 .
Support 3 dtbs.
aml_dt soc: g12a platform: u212 variant: 1g
dtb 0 soc: g12a plat: u212 vari: 1g
dtb 1 soc: g12a plat: u212 vari: 2g
dtb 2 soc: sm1 plat: ac213 vari: 2g
Find match dtb: 0
start dts,buffer=0000000033e3a920,dt_addr=0000000033e3a920
get_partition_from_dts() 92: ret 0
Amlogic multi-dtb tool
Single dtb detected
parts: 21
00: logo 0000000000800000 1
01: recovery 0000000001800000 1
02: misc 0000000000800000 1
03: dtbo 0000000000800000 1
04: cri_data 0000000000800000 2
05: param 0000000001000000 2
06: boot 0000000001000000 1
set has_boot_slot = 0
07: rsv 0000000001000000 1
08: metadata 0000000001000000 1
09: vbmeta 0000000000200000 1
10: tee 0000000002000000 1
11: vendor 0000000014000000 1
12: skmac 0000000000400000 1
13: odm 0000000001000000 1
14: system 0000000050000000 1
15: product 0000000008000000 1
16: ctc 0000000010000000 1
17: skparam 0000000001000000 2
18: skbackup 0000000030000000 2
19: cache 0000000040000000 2
20: data ffffffffffffffff 4
init_part() 297: PART_TYPE_AML
eMMC/TSD partition table have been checked OK!
crc32_s:0x1577dad == storage crc_pattern:0x1577dad!!!
crc32_s:0xee152b83 == storage crc_pattern:0xee152b83!!!
crc32_s:0x79f50f07 == storage crc_pattern:0x79f50f07!!!
mmc env offset: 0x6c00000
In: serial
Out: serial
Err: serial
reboot_mode=normal
[store]To run cmd[emmc dtb_read 0x1000000 0x40000]
_verify_dtb_checksum()-3476: calc 8fee3e9b, store 8fee3e9b
_verify_dtb_checksum()-3476: calc 8fee3e9b, store 8fee3e9b
dtb_read()-3691: total valid 2
update_old_dtb()-3672: do nothing
Amlogic multi-dtb tool
GZIP format, decompress...
Multi dtb detected
Multi dtb tool version: v2 .
Support 3 dtbs.
aml_dt soc: g12a platform: u212 variant: 1g
dtb 0 soc: g12a plat: u212 vari: 1g
dtb 1 soc: g12a plat: u212 vari: 2g
dtb 2 soc: sm1 plat: ac213 vari: 2g
Find match dtb: 0
amlkey_init() enter!
[EFUSE_MSG]keynum is 4
vpu: driver version: v20190313
vpu: detect chip type: 8
vpu: clk_level default: 7(666667000Hz), max: 7(666667000Hz)
vpu: clk_level in dts: 7
vpu: vpu_power_on
vpu: set_vpu_clk
vpu: set clk: 666667000Hz, readback: 666666667Hz(0x100)
vpu: set_vpu_clk finish
vpu: vpu_module_init_config
vpp: vpp_init
vpp: vpp osd2 matrix rgb2yuv..............
hdr_func 4, hdr_process_select 0x1
cvbs: cpuid:0x28
vdac_gsw_init: 0x0
cvbs: find performance_pal config
aml_config_dtb 637
aml_config_dtb 667
co_phase = <0x00000003>
caps2 = "MMC_CAP2_HS200"
f_max = <0x02faf080>
status = "disabled"
status = "okay"
wipe_data=successful
wipe_cache=successful
upgrade_step=2
reboot_mode:::: normal
ext4logoLoadCmd=ext4load mmc 1:${logoPart} ${logoLoadAddr} ${ext4LogoPath}
6220854 bytes read in 179 ms (33.1 MiB/s)
[imgread]load bmp from ext4 part okay
bmp pixel: 24
[OSD]load fb addr from dts:/meson-fb
[OSD]set initrd_high: 0x3f800000
[OSD]fb_addr for logo: 0x3f800000
[OSD]load fb addr from dts:/meson-fb
[OSD]fb_addr for logo: 0x3f800000
[OSD]VPP_OFIFO_SIZE:0xfff01fff
[CANVAS]canvas init
[CANVAS]addr=0x3f800000 width=5760, height=2160
[OSD]osd_hw.free_dst_data: 0,719,0,479
[OSD]osd1_update_disp_freescale_enable
cvbs: outputmode[480p60hz] is invalid
vpp: vpp_matrix_update: 2
set hdmitx VIC = 3
aml_audio_init
config HPLL = 4324320 frac_rate = 0
HPLL: 0x3b0004b4
HPLL: 0x1b0004b4
HPLL: 0xdb0004b4
config HPLL done
j = 1 vid_clk_div = 1
hdmitx: set enc for VIC: 3
hdmitx phy setting done
rx version is 1.4 or below div=10
hdmtix: set audio
hdmi_tx_set: save mode: 480p60hz, attr: rgb,8bit, hdmichecksum:
Saving Environment to aml-storage...
mmc env offset: 0x6c00000
Writing to MMC(1)... done
hdr_packet
vpp: hdr_policy = 2
vpp: Rx hdr_info.hdr_sup_eotf_smpte_st_2084 = 0
time_out = 493e0
key[0] = 66994cb3
key[1] = 6699fd01
key[2] = 6699dd22
irkey - irkey ... - maximum value of N: 10
Usage:
irkey - No additional help available.
time_out = 0
key[0] = 3ec14cb3
key[1] = 3ec1fd01
key[2] = 3ec1dd22
irkey - irkey ... - maximum value of N: 10
Usage:
irkey - No additional help available.
Command: bcb uboot-command
Start read misc partition datas!
BCB hasn't any datas,exit!
rebootmode=normal
Saving Environment to aml-storage...
mmc env offset: 0x6c00000
Writing to MMC(1)... done
Hit Enter or space or Ctrl+C key to stop autoboot -- : 0
card out
(Re)start USB...
USB0: USB3.0 XHCI init start
Register 3000140 NbrPorts 2
Starting the controller
USB XHCI 1.10
scanning bus 0 for devices... 2 USB Device(s) found
scanning usb for storage devices... init_part() 282: PART_TYPE_DOS
1 Storage Device(s) found
reading s905_autoscript
1654 bytes read in 54 ms (29.3 KiB/s)
Executing script at 01020000
start amlogic old u-boot
Error: "bootfromsd" not defined
card out
** Bad device mmc 0 **
reading boot_android
** Unable to read file boot_android **
card out
** Bad device mmc 0 **
reading u-boot.ext
** Unable to read file u-boot.ext **
card out
** Bad device mmc 0 **
start test usb
reading uEnv.txt
327 bytes read in 43 ms (6.8 KiB/s)
mac=A0:4C:0C:04:AD:1F
reading /zImage
27298304 bytes read in 1250 ms (20.8 MiB/s)
reading /uInitrd
17983027 bytes read in 869 ms (19.7 MiB/s)
reading /dtb/amlogic/meson-g12a-s905l3a-e900v22c.dtb
73357 bytes read in 234 ms (305.7 KiB/s)
Error: "aadmac" not defined
libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND
[rsvmem] fdt get prop fail.
Loading init Ramdisk from Legacy Image at 13000000 ...
Image Name: uInitrd
Image Type: AArch64 Linux RAMDisk Image (gzip compressed)
Data Size: 17982963 Bytes = 17.1 MiB
Load Address: 00000000
Entry Point: 00000000
Verifying Checksum ... OK
[store]Is good fdt check header, no need decrypt!
active_slot is normal
load dtb from 0x1000000 ......
Amlogic multi-dtb tool
Single dtb detected
Flattened Device Tree blob at 01000000
Booting using the fdt blob at 0x1000000
find 1 dtbos
No androidboot.dtbo_idx configured
And no dtbos will be applied
libfdt fdt_path_offset() returned FDT_ERR_NOTFOUND
[rsvmem] fdt get prop fail.
Loading Ramdisk to 32d0c000, end 33e325f3 ... OK
Loading Device Tree to 000000001ffeb000, end 000000001fffff42 ... OK
fdt_fixup_memory_banks, reg:000000001fff69d4
DTS already have 'reg' property
Starting kernel ...
uboot time: 7818946 us
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