CircuitVerse
Replies: 30 comments 13 replies
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1. Real-Time Collaborative Circuit DesignCircuitVerse currently has no real-time collaboration. Students cannot pair-program on circuits remotely, and educators cannot co-debug with students live. The existing Collaboration model only stores access permissions, it simply tracks who can view or edit a project, but provides no infrastructure for live, concurrent editing. 2. WebAssembly Backend for High-Performance SimulationJavaScript is 10-100x slower than native code. Complex circuits can cause UI freezes because simulation blocks the main thread. Port simulation engine to Rust or C++, compile to WebAssembly, call from JavaScript. |
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Great Idea and also Web sockets are very interesting to work with! |
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Really like this! Real-time collaboration would be a huge win for teaching and pair-debugging. I’m also particularly interested in the Rust/WebAssembly simulation backend idea — it seems like it could fix a lot of UI freeze issues for large circuits by moving execution off the main thread. Would love to better understand the current simulator architecture — is the logic already isolated enough that a WASM backend could drop in cleanly, or would we first need some refactoring? |
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Man, this would be sick. It is nice that I wanted to learn Web sockets |
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I’m currently focusing on Rust and would really like to align my contributions around a Rust/WebAssembly simulation backend. My goal is to eventually work on a production-grade Rust codebase, so this seems like a great opportunity to both improve performance and gain real-world Rust experience. If the team is open to it, I’d love to start by understanding the simulator module boundaries and see what work would be required to incrementally introduce a Rust → WebAssembly backend (while keeping the existing JS path functional). Any guidance on where to begin in the codebase would be really helpful. |
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check out this if interested Circuitverse real time collaboration demo - https://youtu.be/Ego7l8d3H_A https://github.com/vnydv/cv-frontend-vue-real-time-collab/tree/collab-circuitverse-vue-simulation |
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Prajwal R H , here sharing three focused ideas that extend existing CircuitVerse work; happy to connect and refine these further if they resonate with the team. 1. AI‑Assisted Circuit Tutor & Debugger
2. Verilog‑Powered Project Templates & Auto‑Grader
3. Open Hardware Lab 2.0: Cloud Boards & Shared Experiments
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Hi! David here i'm interested in contributing to CircuitVerse for GSoC and had the following ideas: 1. Waveform Viewer and Step Debugger
2. Enhanced Truth Table to Circuit Generator
I’d appreciate your feedback on whether these align with CircuitVerse’s current priorities. |
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Summary: Idea Today, when circuits grow complex, users often struggle not because of missing features, but because they can’t see or reason about signal propagation and timing. When debugging fails, users must restart the entire simulation, there’s no way to rewind, inspect intermediate states, or explain why a value changed at a specific moment. Problem:
Solution:
Why This Matters:
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1. Circuit Linting & Design Quality Analyzer This project proposes a static analysis (non-simulation) tool for CircuitVerse that evaluates circuit structure and design quality. 2. Interactive In-Editor Learning Mode This project aims to provide guided, step-by-step learning directly within the CircuitVerse editor. |
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Given that GSOC is expanding focus on domains like AI, Security, and Machine Learning. Wouldn't it be better to think on how the platform can be optimized w.r.t the current code convention and environment. |
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Hey everyone! I had the following ideas for this GSOC period, one focused at the circuitverse-end user focused and other on developer experience. 1) Circuitverse-User FocusedThis project proposes a Git-inspired version control system for digital circuit design in CircuitVerse. Unlike text-based version control, it understands circuit components, connections, signal flow, and visual layout. The goal is to enable branching, merging, diffing, and collaboration while remaining intuitive for students and educators. Problems
Proposed ApproachIntroduce a circuit-aware version control layer that stores circuits as structured data instead of flat snapshots. Each version records component changes, wiring updates, layout adjustments, and metadata like author and intent. This enables Git-like workflows such as branching, merging, rollback, and tagged versions. A visual diff system highlights changed gates, wires, and sub-circuits, clearly separating functional and visual changes. Collaboration is improved through permissions, parallel workflows, and conflict-aware merges, all integrated smoothly into existing CircuitVerse usage. Advantages
Disadvantages
2) Developer FocusedThis project improves CircuitVerse’s API development workflow by introducing a Git-native, open-source API testing system built around Bruno. The goal is to replace manual API testing with a structured, version-controlled, and CI-friendly approach. Problems
Proposed ApproachAdopt Bruno as the primary API testing tool. Bruno stores API requests, environments, and tests as plain text files, making them fully Git-versioned and reviewable. API endpoints are organized into structured collections with reusable authentication, environment configs, and automated assertions. Contributors can test APIs locally with minimal setup. Bruno’s CLI enables API tests to run in CI on pull requests, catching breaking changes early. These collections also act as executable API documentation and a base for OpenAPI generation. Advantages
Disadvantages
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Proposed IdeaThis project introduces a constraint-based learning layer in CircuitVerse that helps users design circuits with clear goals and understand real-world design trade-offs. Instead of stopping at functional correctness, users learn to evaluate how good a design is. Constraint DefinitionUsers and educators can define design constraints such as:
Circuit AnalysisCircuitVerse analyzes the circuit using structural analysis and simulation data to compute:
Learning-Focused FeedbackIf a circuit violates one or more constraints, CircuitVerse provides:
The tool does not automatically modify circuits, keeping the learning process student-driven and intentional. Classroom ImpactFor educators, this enables:
Why This MattersThis approach helps students:
By bridging academic circuit design with real-world engineering thinking, this feature would make CircuitVerse a stronger learning platform for both students and educators. |
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Proposed Ideas
OverviewThis idea focuses on using AI in CircuitVerse as a learning support system, not as a shortcut. Many beginners leave the platform because they do not understand why their circuit is not working or how to start building one. These features aim to reduce frustration and help students gain a clearer understanding of digital logic. Idea 1: Context-Aware AI TutorThe ProblemWhen a student builds a circuit and it does not work, the simulator only shows incorrect or no output. In an offline lab, a teacher would look at the circuit and point out the mistake.
The IdeaA context-aware AI tutor that understands the circuit currently open on the canvas. Instead of giving generic answers, the AI:
Practical ExampleA student builds a D Flip-Flop circuit but the output never changes. Student asks:
AI responds:
Impact
Idea 2: Natural Language → Circuit GeneratorThe ProblemBeginners often understand the theory but feel lost when faced with an empty canvas. They know what they want to build but not how to begin. The IdeaAllow users to describe a circuit in simple English, and CircuitVerse generates a basic working circuit as a starting point. The generated circuit is:
Practical Use CaseMany beginners understand digital logic concepts but struggle to start from an empty canvas. With this feature, a student can simply type:
CircuitVerse immediately generates a basic working circuit with the correct components and connections. The student can then:
Why This Is Useful
This feature acts as a learning starting point, not a replacement for understanding. |
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I’ve been going through the GSoC mentor guidelines and also spending time understanding CircuitVerse from both the website and codebase side, especially around the simulator and core execution flow. One thing that stood out to me is that while GSoC this year is encouraging organizations to think about AI-related projects, CircuitVerse’s core philosophy seems very intentionally learning-first and deterministic. The platform’s strength is helping users understand why a circuit behaves a certain way, rather than abstracting that reasoning behind black-box features. With that in mind, I’ve been thinking more about foundational improvements rather than direct AI integration. Debugging today largely involves re-running simulations and visually inferring where things go wrong, which becomes difficult as circuits grow in complexity. There isn’t a clear way to step through execution or inspect signal and component state over time. A step-based, deterministic execution mode with basic signal/state inspection could be a strong building block here. Allowing users to pause, step through ticks, and inspect wire values and component states without rewriting the simulator feels well aligned with CircuitVerse’s educational goals. It also creates structured execution data that future analysis or even AI-assisted explanations could build on later, if the community ever wants to explore that direction. I also noticed that CircuitVerse is built on a Rails stack, which made the overall architecture easier to reason about coming from a MERN-style background. I’ve been getting more comfortable with Rails conventions while reading through the codebase. Just sharing my thoughts would love to know if this direction aligns with what mentors are currently prioritizing. |
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Hi everyone, ProblemAs circuits grow more complex, debugging in CircuitVerse mostly involves re running simulations and visually inferring what went wrong. This makes it hard to understand why a circuit behaves a certain way, especially for sequential circuits, and also makes simulator edge cases harder to reason about. Rough IdeaA possible project direction could be adding an execution transparency and debugging layer to CircuitVerse. In simple terms, this would allow users to:
The goal is not to change how the simulator works internally, but to expose and control execution in a way that improves understanding and debugging. Why this could be useful
Scope (very rough)This could be scoped incrementally:
This is intentionally a high level direction for now. I’d love feedback on:
Thanks! Looking forward to feedback. |
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Hi everyone, OverviewThis project proposes introducing an optional keyboard-first interaction mode for CircuitVerse to improve accessibility and usability for all users. ProblemCircuitVerse is largely mouse-driven and visually dense, which makes it difficult to use for:
Proposed SolutionIntroduce an optional keyboard-first interaction mode for CircuitVerse. Key FeaturesThis would allow users to:
Design PhilosophyThe interaction model would be inspired by tools like Logisim and keyboard-driven menus (e.g., CS-style selection menus). The existing mouse-based workflow would remain completely unchanged. Benefits
ScopeThis is intentionally rough and open to feedback. Proposed deliverables:
This is intentionally Rough for now. I’d love feedback on whether this aligns with CircuitVerse’s priorities and if the scope seems reasonable for a GSoC-sized project. Thanks! |
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Thanks for your suggestion, we already have this feature on the simulator! |
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Hello, Arnab, Jay Mehta Here. Thanks for reaching out. I've gone through the documentation and tried the simulator. I feel like we have a slight misalignment with our ideas ... If possible I would love to discuss this with you on LinkedIn or another platform. PS I've sent you a request on Linkedin, we can chat there if you like. |
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Hi everyone! I’d like to share a rough project idea for GSoC 2026 focused on live teaching and real-time collaboration. ProblemTeaching circuits remotely is tough. Teachers share screens on Zoom while students try to follow along. There's no way to:
Rough IdeaA possible project direction could be adding real-time collaborative sessions to CircuitVerse — a "Virtual Lab" mode. In simple terms, this would allow users to:
The goal is to add a collaborative layer on top of the existing simulator for better remote teaching. Why this could be useful
Scope (rough idea)Core features:
This is intentionally high-level for now. I'd love feedback on:
Thanks! Happy to adjust based on feedback. |
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Hi everyone, sharing a practical project idea based on my understanding of the current codebase. After cloning the repo and going through the JavaScript simulation layer, it’s clear that CircuitVerse models (gates, wires, and nodes) as subclasses of CircuitElement, with rendering and simulation handled entirely on the canvas side. Based on this, I’m interested in building a feature inside the existing JS simulation layer, without changing the simulator internals or the Rails stack. The Concrete Idea is:
From there, the current flow remains unchanged:
The Goal : On top of the generated circuit, this could optionally explain what each component is doing and provide context-aware hints when something is wired incorrectly, mainly as a learning aid. I’d appreciate feedback on whether this direction fits the project goals and which part of the JS simulation layer would be the best place to hook into for programmatic circuit creation. (Optional reference) |
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74LS TTL IC Library for CircuitVerseCircuitVerse currently has basic gates, flip-flops, counters, and some combinational components, but it does not have a complete 74LS TTL IC library. Proposed SolutionIntroduce a dedicated 74LS TTL IC library with the following features:
Benefits
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Idea 1: Analog & Mixed-Signal Simulation ExtensionCore Idea: Problem: Solution: Why It Matters: Idea 2: Hardware Description Language (HDL) Integration for CircuitVerseCore Idea: Problem: Solution: Why It Matters: |
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ML Circuit Debugging Assistant Problem: Students waste 40-60% of time manually debugging timing errors, race conditions, and metastability in CircuitVerse simulations. Solution: Copilot-style chat in Vue UI that analyzes sim logs/netlists, suggests fixes (Verilog patches, UI changes), explains root causes. Tech Stack: Vue.js (frontend), Rails API, Python (ML backend), CodeLlama-7B fine-tuned Why:
Seeking early community approval/feedback on this idea or improvements! thanks, |
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Boosting Community Growth through Enhanced Contests and Onboarding(FAQ section, Testimonials)Hi everyone! I want to propose a project for GSoC 2026 that focuses on making CircuitVerse more engaging for students and easier for teachers to join. 1) Transforming CircuitVerse ContestsCurrently, contests are a great way to engage users, but they can feel overwhelming to beginners. I propose making them more structured and inclusive
2) Social Proof & FeedbackTo show the impact of CircuitVerse, we need to highlight user success:
3) Smart FAQ SectionA structured FAQ section will reduce repetitive support questions and help users get started faster:
Why this is a great GSoC 2026 Project?This project focuses on User Retention. By making the platform more welcoming (FAQ), fair (Tiered Contests), and rewarding (LeetCode-style badges), we can keep the community active and growing. I would love to hear from the mentors: which of these features do you think is the highest priority for the platform right now? Excited to work on them this Summer! |
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Problem Statement: Proposed Solution: Decomposition: Performance Optimization: State Preservation: Standardization: Benefit to Community: |
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AI-Powered Design Assistant: Smart Routing & Predictive DebuggingGoal: Integrate Machine Learning to transition CircuitVerse from a manual tool into a Smart EDA (Electronic Design Automation). OverviewThe project aims to enhance the CircuitVerse simulator by implementing intelligent automation features that assist users in creating cleaner, error-free digital logic designs. 1. RL-Based Auto-Routing
2. Predictive Debugging
3. Impact
🛠️ Technical Proof of Concept (PoC)To keep the tool serverless, I propose using TensorFlow.js for in-browser inference. Below is a simplified logic for contention detection: // Sample logic for real-time error detection
import * as tf from '@tensorflow/tfjs';
async function analyzeCircuit(wiringPattern) {
const model = await tf.loadLayersModel('model/circuit-v-v1.json');
const prediction = model.predict(tf.tensor2d([wiringPattern]));
// If probability of error > 80%, trigger a UI tooltip
if (prediction.dataSync()[0] > 0.8) {
showWarning("Potential Bus Contention Detected!");
}
} |
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Yes, Integrating an AI model would significantly increase efficiency by automating the replication of standard components. This would help reduce time spent on repetitive execution and allows us to dedicate our focus to complex planning and strategy. |
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Project Proposal: CV-SoC Lab — Microcontroller Co-Simulation in CircuitVerseCircuitVerse excels at teaching digital logic design, but many undergraduate courses require students to run real firmware on microcontrollers and observe hardware behavior. There is no unified, browser-based environment where:
Proposed SolutionIntroduce CV-SoC Lab, an in-browser microcontroller co-simulation layer that allows users to attach a virtual microcontroller to CircuitVerse circuits and execute firmware while interacting with existing logic components. This bridges the gap between: Digital logic → Embedded systems → Hardware–software co-design Core Idea Embed a lightweight microcontroller emulator (compiled to WebAssembly) inside CircuitVerse Allow mapping of MCU GPIO pins to circuit nodes Execute firmware (initially pre-compiled binaries) Provide observability via:
Will think about the technical part once the project is approved. Any suggestions are welcomed. |
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Idea: True Timing-Aware (Event-Driven) Simulation in CircuitVerseProblem Statement:CircuitVerse is great for learning logic correctness, but it is still limited when it comes to timing behavior. Right now, CircuitVerse allows users to set a delay value for gates, and this delay is shown in the timing diagram. Because of this:
In real digital circuits, timing matters just as much as logic. Many bugs happen even when the logic is correct, due to unequal propagation delays, races, or clock timing problems. These concepts are difficult to demonstrate using the current simulation model. Proposed Idea:Add an optional event-driven timing simulation mode to CircuitVerse that uses true gate-level propagation delays. In this mode:
The existing simulation mode would remain unchanged, so this would just be an additional mode. Technical Implementation:The idea can be implemented by extending the current simulator with a separate event-driven execution path. In this approach, the simulator maintains a global event queue, where each event represents a signal change along with a timestamp. Whenever a wire or gate output changes, new events are scheduled for the connected components based on their individual delay values. These events are then processed in increasing time order, updating wire and gate states as signals propagate through the circuit. Unlike the current step-based approach, the timing diagram in this mode would be generated directly from the scheduled events, allowing intermediate transitions and ordering effects to be visible. Once this core mechanism is in place, it naturally allows future extensions such as highlighting competing signal paths, visualizing glitches or races, identifying critical paths, or adding simple timing warnings, without changing the existing simulation mode. |
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CircuitVerse Design Review & Feedback System CircuitVerse currently allows sharing and viewing circuits, but meaningful feedback on circuit design happens outside the platform. Instructors and peers cannot annotate specific gates, wires, or subcircuits, making it hard to give precise, actionable feedback or guide iterative improvement. This project proposes a circuit-aware design review system that enables structured, asynchronous feedback directly on the circuit canvas. Reviewers can attach comments to individual components or connections, start discussion threads, and mark feedback as resolved once changes are made. Instructors can optionally use rubric-based evaluation, and peer reviews can be enabled with guided prompts to encourage constructive learning. The goal is to improve how students learn design quality, readability, and reasoning, not just functional correctness, while staying aligned with CircuitVerse’s learning-first philosophy. The system does not modify simulator internals and can be implemented incrementally, making it well-scoped for GSoC. |
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Cloud Sync Architecture Proposal for CircuitVerseProposed Feature:A unified cloud synchronization system for CircuitVerse that bridges the gap between the web simulator and the Tauri desktop application. Currently, both platforms operate on isolated storage models browser localStorage on the web and local filesystem storage on desktop resulting in fragmented project states, version conflicts, and no cross-device continuity. The proposed system introduces a Git-inspired versioned sync model that supports offline-first workflows, automatic merging, and transparent conflict resolution, enabling users to move seamlessly between platforms without data loss. Every project save is treated as a versioned snapshot with metadata (timestamp, device, checksum, parent version), allowing the system to reconstruct history, detect divergence, and safely merge parallel edits. Instead of overwriting data, all changes are reconciled using a common ancestor, preserving intent and preventing silent loss. Versioning ModelEach project save is stored as a discrete version object containing the full project state, a cryptographic checksum, a reference to its parent, and a granular changelog. This allows the system to detect divergence, reconstruct history, and perform three-way merges. Unlike naive timestamp-based syncing, this model is resilient to offline edits, delayed uploads, and multi-device concurrency. This approach also enables future features like rollback, audit trails, collaborative workflows, and project history browsing without additional infrastructure. Conflict Detection & ResolutionConflict detection is based on a three-way diff between the base version, the local version, and the cloud version. Changes are classified structurally (different entities), property-wise (same entity, different fields), or semantically (deletions vs modifications). Non-overlapping changes are auto-merged, while destructive or ambiguous conflicts are escalated to the user. Offline-First DesignThe system is designed to function fully offline. All changes are queued locally and synced once connectivity is restored. This avoids blocking user workflows and ensures no edits are lost due to transient network failures. When reconnection occurs, queued versions are reconciled against the cloud state, triggering conflict resolution only when necessary. This is critical for educational and low-connectivity environments, where reliability matters more than immediacy. Performance StrategyTo maintain responsiveness even for large circuits, the system uses incremental syncing, delta compression, background workers, and debounced autosaves. Instead of transmitting full project blobs on every change, only the affected entities are synced. Conflict data is lazily loaded, and heavy diff operations run off the main UI thread. This ensures scalability without sacrificing interactivity. User ExperienceFrom the user’s perspective, syncing is mostly invisible. Changes auto-save, sync in the background, and appear instantly on other devices. When conflicts occur, they are surfaced clearly with visual diffs and side-by-side comparisons, allowing users to choose, merge, or customize resolutions. The system emphasizes clarity over automation users always know what changed and why. Backend DesignThe backend stores immutable project versions, conflict records, and sync state metadata. This enables traceability, recovery, auditing, and deterministic merging. The API exposes pull, push, conflict resolution, and history endpoints, allowing both web and desktop clients to use the same logic. This structure also makes the system extensible for future features like collaboration, branching, and shared editing. |
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Hi everyone! I’d like to share a rough project idea for GSoC 2026 focused on improving how teachers and students review circuits inside CircuitVerse. problem1)CircuitVerse is great for building and sharing circuits, but reviewing student circuits is difficult
Solution (Project Idea)1)Add a Circuit Review Mode inside CircuitVerse ✅ Pass 3)Allow short notes per checklist item (optional) Keep UI/UX clean: Why it matters1)Makes feedback clear and actionable for students Summary (How CircuitVerse becomes better)1)CircuitVerse becomes more classroom-ready Overall platform becomes more structured, supportive, and scalable for education |
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Idea : Improving Onboarding and Learning Experience in CircuitVerseWhile exploring the CircuitVerse ecosystem, one gap became immediately apparent: the lack of a structured, low-friction onboarding experience for new users, especially first year undergrads. In this environment with declining attention spans and abundant alternatives, the rule of thumb is that if a first-year student can’t build something in 5 minutes, they won’t return. Currently, CircuitVerse offers powerful tools, but the initial learning curve is steep, particularly for students without prior exposure to digital logic concepts (e.g., timing diagrams, signal propagation). The solution is structured around how users naturally enter the platform. You have two types of naive users when it comes to non-educators. 1. Users who directly open the simulator:
Concepts are learned through interaction rather than terminology. For example, a timing diagram is experienced before it is explained. Users understand tools faster when they see why they are needed. This approach lowers cognitive load and helps users build intuition before theory. 2. Users who jump on the interactive textbook
To enhance engagement, this guidance can be delivered via a lightweight interactive guide or mascot, acting as a contextual assistant rather than a static tutorial. The core strength of this proposal is that it does not attempt to teach concepts upfront. Instead, it focuses on guided discovery by meeting users where they are, whether in the stimulator or the texbook. For many beginners, the difference between continuing and abandoning the platform is not motivation or ability, but whether their first five minutes feel empowering or overwhelming. If student can click, simulate, and say “oh, that’s what’s happening” within minutes, they are far more likely to come back. This project is about making that moment happen |
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Core Problem: The "Standard Library" GapWhile CircuitVerse is an excellent educational tool for digital logic, it currently lacks a comprehensive standard library of commercial Integrated Circuits (ICs). As @Nihal4777 mentioned regarding the 74LS TTL library gap, there are also significant gaps in other essential families used in real world electronics education, including:
The Bottleneck: While researching the 74LS series and attempting to build initial chips (like the 7490) by hand, I quickly realized that manually hardcoding pin positions and logic states in JavaScript is error-prone and tedious. I found that the current manual approach is:
Proposed Solution: The "Datasheet-to-Silicon" PipelineTo address these issues, I moved away from manual coding and designed an Automated Component Synthesis Framework. This architecture decouples the chip definition from the simulator implementation, creating a robust data-driven pipeline. The Architecture:1. Input Layer (AI-Assisted):
2. Intermediate Representation (JSON Schema):
3. Generator Engine (The "Compiler"):
4. Runtime Core (IC74 Series Base Class):
3. Proof of Concept: Working 74LS Series ImplementationTo validate this architecture, I focused on the Automation workflow. instead of writing code for every chip, I simply defined the logic in a JSON file and let the script do the heavy lifting. The Workflow I Used:1. Define: Created a single
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Sequential ICs
- 7474 (Dual D-FF), 7476 (Dual JK-FF), 7490 (Decade Counter), 74161 (4-Bit Binary Counter)
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Note: Videos may take 1-2 minutes to load. If you experience playback issues, watch all demonstrations in this YouTube playlist.
Demonstrated Capabilities:
- Single Source of Truth: The entire library is driven by simple JSON files. The JavaScript code is treated as a build artifact.
- Hybrid Logic Simulation: The 7490 Counter implementation demonstrates a robust solution for simulating "Ripple Counters" (Falling Edge) within a discrete-time simulator without race conditions.
- Visual Standardization: All chips use a unified "Dark DIP" visual style with standardized green connection nodes using SVG generation.
- Rapid logical iteration: Changing a chip from Rising Edge to Falling Edge now requires changing one line in the Base Class, instantly updating all derived chips.
4. Benefits & Impact
- 10x Velocity: New chips can be added in minutes (defining JSON) rather than hours (coding JS).
- Maintenance: Bugs in pin alignment or logic propagation are fixed once in the Base Class and propagate to the entire library.
- Accessibility: Enables students to simulate the exact chips they will use in university labs (e.g., "Build a counter using a 7490" assignments)
5. Future Vision:
I think this project sets the stage for a high-impact :
- Phase 1: Expand the Generator to support Analog/Mixed-Signal definitions (for 555 Timers).
- Phase 2: Implement the "AI Datasheet parser" tool to automatically scrape PDF pinouts into our JSON format.
- Phase 3: Roll out the complete 4000 CMOS and 74HC libraries (50+ chips)
- Phase 4: Develop a UI-based "Chip Builder" inside CircuitVerse, allowing users to define custom ICs graphically and export them to the community library.
I believe this infrastructure upgrade is essential for CircuitVerse to compete with desktop tools like Logisim, Tinkercad and Multisim in higher education.
I welcome feedback on this architectural approach!
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Project Idea 1: Instructor Dashboard with Assignment Creation & Auto-GradingProject SummaryCircuitVerse is widely used for teaching digital logic, but instructors currently lack built-in tools to manage courses, create assignments, and evaluate student submissions. This project aims to build a full-fledged Instructor Dashboard that allows educators to create courses and assignments, automatically grade circuit submissions using test cases, and track student performance through analytics. The system will integrate seamlessly with the existing CircuitVerse simulator to provide a smooth classroom workflow without relying on external LMS platforms. Impact
Implementation Plan
Project Idea 2: CircuitVerse Community Hub (Q&A and Circuit Showcase)Project SummaryCircuitVerse currently lacks a centralized community space for users to ask questions, share circuits, and showcase projects. This project proposes building a Community Hub integrated into CircuitVerse, featuring a Q&A forum and a circuit showcase gallery where users can share designs, receive feedback, and learn collaboratively. The goal is to strengthen community engagement and reduce dependency on external platforms for support and discussion. Impact
Implementation Plan
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Weekly Contest 2.0: Automated Technical Judging & GamificationHello maintainers! As the project list for Gsoc 2026 has been out , I genuinely feel this project should be a part of the list.In the year 2022 @vedant-jain03 initiated the Proof of Concept for Weekly Contests. (https://blog.circuitverse.org/posts/vedant_jain_final_report/) details are mentioned here , in 2024 @Asrani-Aman built the Primary Infrastructure, focusing on making the contest feature accessible and stable. (https://blog.circuitverse.org/posts/aman_asrani_gsoc24_final_report/ ) and in 2025 @salmoneatenbybear made the feature Production-Ready also delivered the public Leaderboard and introduced Internationalization (i18n) support. (https://blog.circuitverse.org/posts/gsoc-2025-project-1-final-report-project-1/)Now it's the time to make the Weekly Contest feature more engaging and smart! I want to propose 'Contest 2.0', focusing on Automated Technical Judging (using the Testbench) and Tiered Skill Tracks. This would turn contests into a true hackathon-style experience with objective ranking based on gate efficiency and correctness.1.Gamification & Admin ControlTheme based Contest : Allow Admin to set custom names, banners, and markdown-based "Problem Statements" (addressing #5998, #6010). Tiered Categories : To maximize engagement, I propose splitting contests into three distinct tracks: Beginner , Intermediate and Advanced For example, Beginner ("Build a Full Adder using only NAND gates") , Intermediate (Build Traffic Light Controllers" or "ALUs") Advanced (Build MIPS Processor Design) 2.Integrity & Fair PlayFork-Blocking : Restrict submissions to original circuits only (checking parent_id). #6009 3.Automated Judging & Efficiency MetricsAuto-Grader : Mentors define a set of test vectors (inputs/outputs). When a user submits, the backend simulates the circuit and checks for logical correctness. Efficiency Metrics (The "Judge") : Rank users not just on "Correctness," but on engineering efficiency: 4.Integration of Group-Specific Visibility (#5942)Classroom Hackathon : By finishing the group-specific visibility, a professor could host a "Private Contest" just for their 2nd-year Digital Logic class. This significantly increases the utility of CircuitVerse for educational institutions. The current weekly contest is functional but static. By implementing these changes it can be more appealing and interesting. I hope this project idea fits for GSOC 2026. |
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Circuit Performance Profiler & Complexity ExplorerMotivation CircuitVerse is a powerful educational digital logic simulator, but students and educators currently lack insight into why certain circuits behave slowly or become confusing at scale. In real hardware design and EDA tools, complexity and performance metrics are core to understanding, debugging, and optimizing a design. ⸻ Summary Introduce a deterministic simulation with time-travel debugging in CircuitVerse, allowing users to step forward and backward through simulation time, inspect historical circuit states, and visually understand signal propagation in complex digital circuits. ⸻ Idea As circuits grow in size and complexity, debugging in CircuitVerse becomes increasingly difficult—not due to lack of features, but due to lack of visibility. Users cannot easily reason about when and why a signal changed. Currently, debugging often involves restarting the simulation repeatedly and visually guessing the source of errors. There is no way to rewind execution, inspect intermediate states, or understand timing interactions step-by-step. This makes learning sequential logic, timing behavior, and signal propagation unnecessarily hard for students. This project proposes adding a deterministic execution and time-travel debugging layer to the simulator to make circuit behavior transparent, explorable, and educational. ⸻ Problem ⸻ Solution Core Features Optional / Later Phase ⸻ Why This Matters |
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This already alligns with my project idea and also project -5 |
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Yes, it’s in the same direction, but this is a more expanded version. |
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I guess it would be better if you look for another idea that can be selected as Project 7.
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This thread has been created for gathering project ideas for GSoC 2026. You can suggest your ideas in this thread. Let's brainstorm and come up with innovative ideas together! 🚀
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