rp2040 PIO limit pins used for sideset

[John1900]

rp2040 PIO Sideset shares the 5 bits normally available for delay. The default limits the delay to [7]. Is there a way to restrict the sideset to 1 pin so delay can go to [15]? Could find nothing in documentation Thanks

[rkompass]

I post a pice of code where the comments tell it:

    # By specifying a pair of values for sideset_init we reserve 2 of the 5 delay/side-set bits for sideset.
    # We have to take care that every instruction has a .side() instruction added, otherwise another bit is reserved for enabling the side-set
    #    thus reducing the maximum delay to 3 instead of 7.
    @asm_pio(sideset_init=(PIO.OUT_LOW, PIO.OUT_LOW), in_shiftdir=PIO.SHIFT_LEFT, out_shiftdir=PIO.SHIFT_RIGHT)
    def sm_qgen():
        nop()                  .side(0b00)        #    so that we can start by setting PC to 0.
        nop()                  .side(0b00)        #
        nop()                  .side(0b00)        # Reason: The instruction memory is filled top-down when the state machine is loaded.
        nop()                  .side(0b00)        #
        label("st_d")
        jmp(y_dec, "st_d")     .side(0b00)  [7]
        # ---------------------
        label("loop")
        mov(osr, isr)          .side(0b00)        # The count variable for the inner loops in ISR is moved to OSR to be consumed by out()'s.
        out(y, 4)              .side(0b00)        # 4 bit count bx_on
        label("bXon")
        jmp(y_dec, "bXon_st")  .side(0b01)  [0]

... so by analogy setting sideset_init=PIO.OUT_LOW should restrict sideset to 1 pin, because this is only one single init value.
However you have to sideset every instruction (except labels of course, which later will not serve as instructions), otherwise
another of the 5 bits is used as the enable bit of the sideset.
I'm not sure the latter is in the docs.

[DrMumurmular]

yup that is the answer