PIO conditional jump based on fifo value

[hanshuebner]

Hi,

I'm working on a parallel interface implementation using PIO and I'm looking for advice on a particular issue. The RP2040 is talking to another device using an 8 bit parallel port with a DIRection and a STroBe signal. The RP2040 is controlling the interface (i.e. it can inititate reads and writes to registers on the other device), but the other device is providing the CLocK. Reading and writing are initiated in the same way: The Python program sends a 32 bit word to the PIO FIFO, with the lower 16 bits containing the bit states for the outputs and the upper 16 bits containing the direction (see code below). Now, for a read operation, the state machine waits for the falling clock edge before sampling the data bits and sending them to the RX fifo. For writing, the read part is not needed and I'd like to skip it. Is there a good way to achieve this by looking at the DIR bit of the command word read from the FIFO? It does not appear to be directly possible, but maybe someone has a clever idea how I can skip the read and push for write operations?

Thanks a lot!
Hans

from machine import Pin
import rp2
from rp2 import PIO

# Pin assignments
PIN_DATA = [Pin(i, Pin.IN) for i in range(2, 10)]
PIN_CLK = Pin(10, Pin.IN)
PIN_DIR = Pin(11, Pin.OUT, Pin.PULL_DOWN)
PIN_STB = Pin(12, Pin.OUT, Pin.PULL_DOWN)
PIN_ADDR = [Pin(i, Pin.OUT) for i in range(13, 16)]

ADDR_BITS_POS = 11 # relative to pin 2

# Bit mask for 32 bit FIFO data.  The upper half defines the direction
# bits, the lower half defines the data bits.  DIR, STB and the ADDR
# bits are always configured as outputs.  When writing, the data bits
# are also configured as outputs, and the DIR bit is set to one.
STB_MASK   = 0b00111110_00000000_00000100_00000000
WRITE_MASK = 0b00000000_11111111_00000010_00000000

# Define the PIO program
@rp2.asm_pio(out_shiftdir=PIO.SHIFT_RIGHT,
             out_init=(PIO.IN_LOW,)*8 + (PIO.IN_LOW, PIO.OUT_LOW, PIO.OUT_LOW) + (PIO.OUT_LOW,)*3,
             autopush=False, autopull=False)
def parallel_interface():
    CLK_PIN = 8 # (GP10)
    # Pull 32-bit value from FIFO
    pull()

    # Wait for rising edge on CLK
    wait(0, pin, CLK_PIN)
    wait(1, pin, CLK_PIN)

    # Output data bits to pins (DATA, CLK, DIR, STB, ADDR + extra)
    out(pins, 16)
    # Output pindirs bits to set pin directions
    out(pindirs, 16)

    # Wait for falling edge on CLK
    wait(0, pin, CLK_PIN)

    # *** These two instructions are not needed for write operations ***
    # Read 8 bits from input pins to ISR.
    in_(pins, 8)
    # Push ISR content to FIFO
    push()

    # Wait for next rising CLK edge to complete cycle
    wait(1, pin, CLK_PIN)

    # Set all outputs to zero
    mov(osr, null)
    out(pins, 16)
    # Set all pindirs to zero (input)
    out(pindirs, 16)

[rkompass]

You might use the jmp(cond, label) statement documented here.
Of course this requires some preparation as for example with the condition not_x you have to compute your logical condition to be in the x register in a negated way. With the PIO instructions available...

[hanshuebner]

@rkompass As the PIO does not have arithmetic instructions that'd allow me to extract individual bits from the FIFO data, I don't see an immediately obvious way to achieve what I'm looking for. I've seen a couple of clever and creative solutions with PIO blocks, however, so I'm hoping that someone smarter than me can give me a hint. If all fails, I can still use separate state machines for reading and writing, and maybe that is even the best way.

[hanshuebner]

... and sometimes, it helps to just spell out the problem to find a solution. I think I can use this MSB of the command word as a read/write indicator, as I only have to control 14 GPIO pins:

    READ_MASK = 0b10000000_00000000_00000000_00000000

and

    # Output data bits to pins (DATA, CLK, DIR, STB, ADDR + extra)
    out(pins, 16)
    # Output pindirs bits to set pin directions (MSB of command word is read/write indicator)
    out(pindirs, 15)

    # Wait for falling edge on CLK
    wait(0, pin, CLK_PIN)

    # Skip reading for write cycle (MSB = 0)
    mov(x, osr)
    jmp(not_x, "finish_cycle")

    # Read 8 bits from input pins to ISR.
    in_(pins, 8)
    # Push ISR content to FIFO
    push()

    label("finish_cycle")
    # Wait for next rising CLK edge to complete cycle
    wait(1, pin, CLK_PIN)

Thank you for reading along!