RP2: Generating Sinewaves with PIO block - without the CPU involved...

[mungewell]

How it started:

How it ended:

import rp2
from machine import Pin
from utime import sleep

# preset pins as inputs, with pull resitors set up/down
Pin(0, Pin.IN, Pin.PULL_UP)
Pin(1, Pin.IN, Pin.PULL_DOWN)

@rp2.asm_pio(sideset_init=[rp2.PIO.IN_HIGH, rp2.PIO.IN_LOW],
         set_init=[rp2.PIO.IN_HIGH, rp2.PIO.IN_LOW])

def pio_sine():							# GPIO1, 		GPIO0
    set(pindirs, 0b11) .side(0b01)		# Low, 			High
    set(pindirs, 0b01) .side(0b01)		# In-pull Low, 	High
    set(pindirs, 0b11) .side(0b11)		# High, 		High
    set(pindirs, 0b01) .side(0b01)		# In-pull Low, 	High
    set(pindirs, 0b11) .side(0b01)		# Low,			High
    set(pindirs, 0b10) .side(0b00)		# Low,			In-Pull High
    set(pindirs, 0b11) .side(0b00)		# Low,			Low
    set(pindirs, 0b10) .side(0b00)		# Low,			In-Pull High


test_sm = rp2.StateMachine(0, pio_sine, freq=5000, sideset_base=Pin(0), set_base=Pin(0))
test_sm.active(1)

while True:
    sleep(10)

So what am I doing?

Whilst looking at how I could remove some IC's from my project's custom board, I was looking how resistors could be connected in special/weird ways. I noticed that the OutputEnable can be written by the PIO blocks, and this combined with 'side-set' can mean that we can switch both the output and output enable at exactly the same way.

If you connect two resistors to two GPIO outputs and then connect the other ends together, you can (ab)use the pull-up and pull-down resistors to generate intermediate voltages; and those voltages can be 'sine like'.

In theory you can calculate the value for 'R', but brute forcing from the resistor store may be more effective... I got close with a limited supply.

Why...?

Now the PIO blocks can be used directly clocked from the division of the SYS clock, and this would also open the possibility of FSK or PSK from a bitstream sent in a FIFO.

You can have multiple PIOs 'communicating' through there out pins and IRQs, I have project where one PIO streams to a out pin, and another sync'ed PIO takes that and encodes it to (basically) manchester encoding... works really nicely AND no CPU involved. I can acutally put CPU into lightsleep() and have the PIOs continue their work - as long as the FIFO doesn't empty completely.

[mendenm]

Of course, what you really want is an inverting, virtual-ground input to an op-amp, so it is a true current-to-voltage converter (transresistance amplifier). Then, you have a nice, simple DAC, and can just use a series of power-of-two resistors to the pads. Although a real DAC would be better, this would certainly give a low component count for cases where you don't need high resolution or accuracy.

[mungewell]

Yes, one could use a resistor-ladder, or a real DAC IC... but where's the fun in that? ;-)

I'm freely admit my brain works weird, and I get enjoyment out of minimal/funky implementations. Once the 'my' output is is low-pass filtered it actually looks OK. The 3rd harmonic is around -39dB down.

000101_0078.wav.zip

[mendenm]

It's really surprising how bad a waveform can be filtered to a sine wave. 'Modified sine wave' power inverters are just square waves with a modified duty cycle (positive, off, negative, off). The third harmonic content of this waveform actually is fairly low, and it can be set to have the right peak-to-peak amplitude of a real sine wave. It looks terrible on a scope, but works better than one might expect! Your few-bit version is actually really good.

I see in your IRIG post below that MSW is what you are doing.

[mungewell]

You can see that there's ringing on the steps, though I don't see this in the scope plot... I think that there is some interaction with my audio recorder. I attempted to add some PSU capacitance to the 'voltage follower' and improved it a bit, but ultimately it's still there. Probably a build error in my tiny SMD circuit....

I think the 3rd harmonic is 'good' as this scheme drives a zero crossing point, it's managing to drive 5 different levels to produce the 'sine'. Even unfiltered it's -35dB down from fundamental.

[mungewell]

As well as FSK and PSK, you can futher abuse the low(er) level to do ASK... this was some experimentation with IRIG that I did today.
irig_test.py.txt

[jean-claudeF]

Wow, that's a surprising + interesting idea!
Do you use it for musical purposes?

[mungewell]

I am more interested in DataComs; the commenting about 'harmonics' is that these (normally) cause unwanted transmissions, and mean that you are using power for signals other than intended.