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Merge pull request #114 from os-fpga/pass_sim_1.5.1
Pulling SIMs release 1.5.1 into main.
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‎blackbox_models/cell_sim_blackbox.v

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@@ -582,6 +582,42 @@ module LUT6 #(
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endmodule
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`endcelldefine
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//
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// MIPI_RX black box model
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// MIPI Receiver
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//
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// Copyright (c) 2024 Rapid Silicon, Inc. All rights reserved.
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//
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`celldefine
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(* blackbox *)
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module MIPI_RX #(
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parameter WIDTH = 4, // Width of input data to serializer (3-10)
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parameter EN_IDLY = "FALSE", // True or False
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parameter DELAY = 0 // Fixed TAP delay value (0-63)
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) (
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input logic RST,
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input logic RX_CLK,
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input logic PLL_LOCK,
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(* clkbuf_sink *)
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input logic CLK_IN,
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input logic RX_DP,
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input logic RX_DN,
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input logic HS_EN,
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input logic LP_EN,
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input logic RX_TERM_EN,
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input logic BITSLIP_ADJ,
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input logic DLY_LOAD,
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input logic DLY_ADJ,
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input logic DLY_INCDEC,
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output logic [5:0] DLY_TAP_VALUE,
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output logic [WIDTH-1:0] HS_RX_DATA,
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output logic HS_RXD_VALID,
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output logic RX_OE,
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output logic LP_RX_DP,
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output logic LP_RX_DN
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);
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endmodule
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`endcelldefine
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//
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// MIPI_TX black box model
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// MIPI Transmitter
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//

‎sim_models/verilog/MIPI_RX.v

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`timescale 1ns/1ps
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`celldefine
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//
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// MIPI_RX simulation model
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// MIPI Receiver
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//
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// Copyright (c) 2023 Rapid Silicon, Inc. All rights reserved.
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//
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module MIPI_RX #(
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parameter WIDTH = 4, // Width of input data to serializer (3-10)
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parameter EN_IDLY = "FALSE", // True or False
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parameter DELAY = 0 // Fixed TAP delay value (0-63)
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) (
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input RST, // Active-low, asynchronous reset
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input RX_CLK, // MIPI RX_IO clock input, PLL_CLK
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input PLL_LOCK, // PLL lock input
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input CLK_IN, // Fabric core clock input
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input RX_DP, // MIPI RX Data Positive input From I_BUF
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input RX_DN, // MIPI RX Data Negative input from I_BUF
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input HS_EN, // EN HS Data input (From Fabric). Active high signal. This is a common signal between MIPI RX/TX interface.
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input LP_EN, // EN LP Data input (From Fabric). This is a common signal between MIPI RX/TX interface.
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input RX_TERM_EN, // EN Differential Termination
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input BITSLIP_ADJ, // BITSLIP_ADJ input from Fabric
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input DLY_LOAD, // Delay load input, from Fabric
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input DLY_ADJ, // Delay adjust input, from Fabric
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input DLY_INCDEC, // Delay increment / decrement input, from Fabric
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output [5:0] DLY_TAP_VALUE, // Delay tap value output to fabric
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output [WIDTH-1:0] HS_RX_DATA, // HS RX Data output to Fabric
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output HS_RXD_VALID, // HS RX Parallel DATA is VALID
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output RX_OE, // IBUF OE signal for MIPI I_BUF
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output LP_RX_DP, // LP RX Data positive output to the Fabric
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output LP_RX_DN // LP RX Data negative output to the Fabric
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);
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wire i_delay_out;
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wire rx_dp_delay;
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wire rx_dn_delay;
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wire rx_dp;
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wire rx_dn;
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I_DELAY # (
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.DELAY(DELAY)
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)
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I_DELAY_inst (
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.I(RX_DP),
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.DLY_LOAD(DLY_LOAD),
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.DLY_ADJ(DLY_ADJ),
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.DLY_INCDEC(DLY_INCDEC),
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.DLY_TAP_VALUE(DLY_TAP_VALUE),
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.CLK_IN(CLK_IN),
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.O(i_delay_out)
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);
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I_SERDES # (
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.DATA_RATE("DDR"),
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.WIDTH(WIDTH),
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.DPA_MODE("NONE")
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)
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I_SERDES_inst (
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.D(rx_dp),
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.RST(RST),
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.BITSLIP_ADJ(BITSLIP_ADJ),
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.EN(HS_EN),
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.CLK_IN(CLK_IN),
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.CLK_OUT(CLK_OUT),
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.Q(HS_RX_DATA),
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.DATA_VALID(HS_RXD_VALID),
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.DPA_LOCK(),
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.DPA_ERROR(),
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.PLL_LOCK(PLL_LOCK),
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.PLL_CLK(RX_CLK)
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);
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assign RX_OE= HS_EN | LP_EN;
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assign rx_dp_delay = (EN_IDLY=="FALSE")? RX_DP:i_delay_out;
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assign rx_dn_delay = (EN_IDLY=="FALSE")? RX_DN:~i_delay_out;
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assign rx_dp = RX_TERM_EN?1'bz:RX_OE?rx_dp_delay:'b0;
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assign rx_dn = RX_TERM_EN?1'bz:RX_OE?rx_dn_delay:'b0;
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assign LP_RX_DP = rx_dp;
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assign LP_RX_DN = rx_dn;
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always@(*)
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begin
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if(LP_EN && HS_EN)
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$fatal(1,"\nERROR: MIPI RX instance %m LP_EN and HS_EN can't be hight at same time");
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end
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initial begin
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if ((WIDTH < 3) || (WIDTH > 10)) begin
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$fatal(1,"MIPI_RX instance %m WIDTH set to incorrect value, %d. Values must be between 3 and 10.", WIDTH);
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end
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case(EN_IDLY)
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"TRUE" ,
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"FALSE": begin end
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default: begin
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$fatal(1,"\nError: MIPI_RX instance %m has parameter EN_IDLY set to %s. Valid values are TRUE, FALSE\n", EN_IDLY);
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end
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endcase
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if ((DELAY < 0) || (DELAY > 63)) begin
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$fatal(1,"MIPI_RX instance %m DELAY set to incorrect value, %d. Values must be between 0 and 63.", DELAY);
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end
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end
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endmodule
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`endcelldefine

‎sim_models/verilog/MIPI_TX.v

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`timescale 1ns/1ps
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`celldefine
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//
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// MIPI_TX simulation model
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// MIPI Transmitter
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//
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// Copyright (c) 2023 Rapid Silicon, Inc. All rights reserved.
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//
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module MIPI_TX #(
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parameter WIDTH = 4, // Width of input data to serializer (3-10)
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parameter EN_ODLY = "FALSE", // True or False
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parameter LANE_MODE = "Master", // Master or Slave
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parameter DELAY = 0 // Fixed TAP delay value (0-63)
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) (
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input RST, // Active-low, asynchronous reset
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input RX_CLK, // MIPI RX_IO clock input, PLL_CLK
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input PLL_LOCK, // PLL lock input
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input CLK_IN, // Fabric core clock input
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input [WIDTH-1:0] HS_TX_DATA, // Parallel Data input bus from fabric
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input HS_TXD_VALID, // Load word input from Fabric
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input HS_EN, // EN HS Data Transmission (From Fabric)
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input TX_LP_DP, // LP TX Data positive from the Fabric
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input TX_LP_DN, // LP TX Data negative from the Fabric
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input LP_EN, // EN LP Data Transmission (From Fabric). Active high signal. This is a common signal between MIPI RX/TX interface.
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input TX_ODT_EN, // EN Termination
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input DLY_LOAD, // Delay load input, from Fabric
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input DLY_ADJ, // Delay adjust input, from Fabric
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input DLY_INCDEC, // Delay increment / decrement input, from Fabric
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output TX_OE, // IBUF OE signal for MIPI O_BUF
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output TX_DP, // Serial Data output to O_BUF
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output TX_DN, // Serial Data output to O_BUF
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input CHANNEL_BOND_SYNC_IN, // Channel bond sync input
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output CHANNEL_BOND_SYNC_OUT // Channel bond sync output
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);
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wire o_serdes_dout;
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wire o_delay_dout;
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O_SERDES # (
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.DATA_RATE("DDR"),
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.WIDTH(WIDTH)
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)
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O_SERDES_inst (
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.D(HS_TX_DATA),
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.RST(RST),
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.DATA_VALID(HS_TXD_VALID),
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.CLK_IN(CLK_IN),
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.OE_IN(),
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.OE_OUT(),
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.Q(o_serdes_dout),
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.CHANNEL_BOND_SYNC_IN(CHANNEL_BOND_SYNC_IN),
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.CHANNEL_BOND_SYNC_OUT(CHANNEL_BOND_SYNC_OUT),
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.PLL_LOCK(PLL_LOCK),
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.PLL_CLK(RX_CLK)
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);
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O_DELAY # (
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.DELAY(DELAY)
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)
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O_DELAY_inst (
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.I(tx_dp),
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.DLY_LOAD(DLY_LOAD),
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.DLY_ADJ(DLY_ADJ),
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.DLY_INCDEC(DLY_INCDEC),
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.DLY_TAP_VALUE(),
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.CLK_IN(CLK_IN),
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.O(o_delay_dout)
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);
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reg tx_dp;
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reg tx_dn;
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assign TX_OE = LP_EN | HS_EN;
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always @(*)
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begin
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if(HS_EN && TX_OE)
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begin
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tx_dp = o_serdes_dout;
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tx_dn = ~tx_dp;
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end
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else if (LP_EN && TX_OE)
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begin
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tx_dp = TX_LP_DP;
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tx_dn = TX_LP_DN;
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end
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end
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assign TX_DP = TX_ODT_EN?1'bz:(EN_ODLY=="FALSE")? tx_dp:o_delay_dout;
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assign TX_DN = TX_ODT_EN?1'bz:(EN_ODLY=="FALSE")? tx_dn:~o_delay_dout;
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// assign TX_DP = tx_dp;
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// assign TX_DN = tx_dn;
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always@(*)
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begin
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if(LP_EN && HS_EN)
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$fatal(1,"\nERROR: MIPI TX instance %m LP_EN and HS_EN can't be hight at same time");
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end
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initial begin
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if ((WIDTH < 3) || (WIDTH > 10)) begin
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$fatal(1,"MIPI_TX instance %m WIDTH set to incorrect value, %d. Values must be between 3 and 10.", WIDTH);
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end
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case(EN_ODLY)
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"TRUE" ,
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"FALSE": begin end
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default: begin
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$fatal(1,"\nError: MIPI_TX instance %m has parameter EN_ODLY set to %s. Valid values are TRUE, FALSE\n", EN_ODLY);
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end
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endcase
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case(LANE_MODE)
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"Master" ,
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"Slave": begin end
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default: begin
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$fatal(1,"\nError: MIPI_TX instance %m has parameter LANE_MODE set to %s. Valid values are Master, Slave\n", LANE_MODE);
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end
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endcase
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if ((DELAY < 0) || (DELAY > 63)) begin
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$fatal(1,"MIPI_TX instance %m DELAY set to incorrect value, %d. Values must be between 0 and 63.", DELAY);
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end
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end
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endmodule
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`endcelldefine

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