Merge pull request #441 from os-fpga/task/EDA-3187/add_setup_lec_sim

EDA-3187 add setup lec sim

Author: NadeemYaseen

RTL_testcases/RTL_Benchmarks_Gap_Analysis/doc_ip_litex/raptor_run.sh

@@ -259,6 +259,9 @@ parse_cga exit 1; }
         else
             echo ""
         fi
+    echo "setup_lec_sim">>raptor_tcl.tcl  
+    [ "$tool_name" = "iverilog" ] && echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl 
+    [ "$tool_name" = "iverilog" ] && echo "simulate pnr icarus">>raptor_tcl.tcl || echo "simulate pnr verilator">>raptor_tcl.tcl 
     echo "sta">>raptor_tcl.tcl  
     echo "power">>raptor_tcl.tcl  
     echo "bitstream $bitstream">>raptor_tcl.tcl  
@@ -272,6 +275,8 @@ parse_cga exit 1; }
         fi
     fi
 
+    [ -f rtl/sim.v ] && sed -i -e "s|MEM_FILE_PATH|$PWD/rtl|g" rtl/sim.v
+
     cd results_dir
     echo "Device: $device">>results.log
     echo "Strategy: $strategy">>results.log

RTL_testcases/RTL_Benchmarks_Gap_Analysis/doc_ip_litex/rtl/sim.v

@@ -1405,7 +1405,7 @@ end
 // Port 0 | Read: Sync  | Write: ---- | 
 reg [31:0] mem[0:5393];
 initial begin
-	$readmemh("mem.init", mem);
+	$readmemh("MEM_FILE_PATH/mem.init", mem);
 end
 reg [31:0] mem_dat0;
 always @(posedge sys_clk_1) begin
@@ -1420,7 +1420,7 @@ assign main_simsoc_dat_r = mem_dat0;
 // Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
 reg [31:0] mem_1[0:874];
 initial begin
-	$readmemh("mem_1.init", mem_1);
+	$readmemh("MEM_FILE_PATH/mem_1.init", mem_1);
 end
 reg [9:0] mem_1_adr0;
 always @(posedge sys_clk_1) begin
@@ -1443,7 +1443,7 @@ assign main_ram_dat_r = mem_1[mem_1_adr0];
 // Port 0 | Read: Sync  | Write: ---- | 
 reg [7:0] mem_2[0:36];
 initial begin
-	$readmemh("mem_2.init", mem_2);
+	$readmemh("MEM_FILE_PATH/mem_2.init", mem_2);
 end
 reg [5:0] mem_2_adr0;
 always @(posedge sys_clk_1) begin
@@ -1458,8 +1458,8 @@ assign builder_csr_bankarray_dat_r = mem_2[mem_2_adr0];
 // Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 10 
 // Port 1 | Read: Sync  | Write: ---- | 
 reg [9:0] storage[0:15];
-reg [9:0] storage_dat0;
-reg [9:0] storage_dat1;
+reg [9:0] storage_dat0=10'd0;
+reg [9:0] storage_dat1=10'd0;
 always @(posedge sys_clk_1) begin
 	if (main_uart_tx_fifo_wrport_we)
 		storage[main_uart_tx_fifo_wrport_adr] <= main_uart_tx_fifo_wrport_dat_w;

RTL_testcases/RTL_Benchmarks_Gap_Analysis/down_counter/raptor_run.sh

@@ -258,6 +258,9 @@ parse_cga exit 1; }
         else
             echo ""
         fi
+    echo "setup_lec_sim">>raptor_tcl.tcl  
+    [ "$tool_name" = "iverilog" ] && echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl 
+    [ "$tool_name" = "iverilog" ] && echo "simulate pnr icarus">>raptor_tcl.tcl || echo "simulate pnr verilator">>raptor_tcl.tcl 
     echo "sta">>raptor_tcl.tcl  
     echo "power">>raptor_tcl.tcl  
     echo "bitstream $bitstream">>raptor_tcl.tcl  

RTL_testcases/RTL_Benchmarks_Gap_Analysis/down_counter/rtl/param_down_counter.v

@@ -13,7 +13,7 @@ module param_down_counter (clk_counter, q_counter, rst_counter);
     input clk_counter;
     input rst_counter;
     output [`size-1:0] q_counter;
-    reg [`size-1:0] q_counter ='b0;
+    reg [`size-1:0] q_counter =5'h1F;
 
     always @ (posedge clk_counter or posedge rst_counter)
 

RTL_testcases/RTL_Benchmarks_Gap_Analysis/dpll-isdn/raptor_run.sh

@@ -262,6 +262,9 @@ parse_cga exit 1; }
         else
             echo ""
         fi
+    echo "setup_lec_sim">>raptor_tcl.tcl  
+    [ "$tool_name" = "iverilog" ] && echo "simulate gate icarus">>raptor_tcl.tcl || echo "simulate gate verilator">>raptor_tcl.tcl 
+    [ "$tool_name" = "iverilog" ] && echo "simulate pnr icarus">>raptor_tcl.tcl || echo "simulate pnr verilator">>raptor_tcl.tcl 
     echo "sta">>raptor_tcl.tcl  
     echo "power">>raptor_tcl.tcl  
     echo "bitstream $bitstream">>raptor_tcl.tcl  

RTL_testcases/RTL_Benchmarks_Gap_Analysis/dpll-isdn/rtl/freqdivider.v

@@ -17,8 +17,8 @@ parameter DividerLength   = 7;
 
 parameter DividerMaxValue = 48;
 
-reg [DividerLength-1 : 0] DividerCounter;
-reg FrequencyOut;        // registered output
+reg [DividerLength-1 : 0] DividerCounter = {DividerLength{1'b0}};
+reg FrequencyOut = 0;        // registered output
 
 /* Process of freq. division according to  signals from Random  Deviations Filter:  */
 /* if "lag" then counter will incremented by 2                                                                          */

RTL_testcases/RTL_Benchmarks_Gap_Analysis/dpll-isdn/rtl/randomwalkfilter.v

@@ -11,7 +11,7 @@ parameter FilterMaxValue    = FilterResetValue;
 parameter FilterMinValue    = 256 - FilterResetValue;
 
 /* reversive counter */ 
-reg [FilterLength-1 : 0] FilterCounter;
+reg [FilterLength-1 : 0] FilterCounter = {FilterLength{1'b0}};
 
 /* calculation of output pulses synchrinized with MainClock */
 always @(posedge MainClock)
@@ -27,7 +27,8 @@ always @(posedge MainClock)
 
 /* making "Lead" and "Lag" signals when  */
 /* counter reached max or min levels     */
-reg Positive, Negative;
+reg Positive = 0;
+reg Negative = 0;
 always @(posedge MainClock)
  begin
   Positive <= (FilterCounter == FilterMaxValue);

RTL_testcases/RTL_Benchmarks_Gap_Analysis/dpll-isdn/rtl/variableresetrandomwalkfilter.v

@@ -20,7 +20,7 @@ parameter ResetterCounterMaxValue = 3;
 parameter ResetterCounterMinValue = 16 - 3;
 
 /* counter "N - RandomWalkFilter" */ 
-reg [N_FilterLength-1 : 0] N_FilterCounter;
+reg [N_FilterLength-1 : 0] N_FilterCounter = {N_FilterLength{1'b0}};
 
 /* connections of "M - RandomWalkFilter" */
 wire Up, Down;
@@ -77,7 +77,8 @@ always @(posedge MainClock)
 
 /* making "Lead" and "Lag" signals when  */
 /* counter reached max or min levels     */
-reg Positive, Negative;
+reg Positive = 0;
+reg Negative = 0;
 always @(posedge MainClock)
  begin
   Positive <= (N_FilterCounter == N_FilterMaxValue);