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lines changedSubmodule FPGA_PRIMITIVES_MODELS updated 13 files
- blackbox_models/cell_sim_blackbox.v-32
- sim_models/tb/DLY_SEL_DECODER_tb.v-65
- sim_models/tb/DLY_VALUE_MUX_tb.v-60
- sim_models/tb/FIFO36K_tb.v+156-1.8k
- sim_models/tb/MIPI_RX_tb.v-167
- sim_models/tb/MIPI_TX_tb.v-109
- sim_models/tb/SOC_FPGA_INTF_DMA_tb.v-83
- sim_models/verilog/DLY_SEL_DCODER.v-33
- sim_models/verilog/DLY_VALUE_MUX.v-19
- sim_models/verilog/FIFO36K.v+45-111
- tb/DLY_SEL_DECODER/DLY_SEL_DECODER_tb.v-65
- tb/DLY_VALUE_MUX/DLY_VALUE_MUX_tb.v-60
- tb/FIFO36K/FIFO36K_tb.v+156-1.8k
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