@@ -5829,6 +5829,44 @@ static void show_sig(const RTLIL::SigSpec &sig)
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run (" write_verilog -org-name -noattr -noexpr -nohex after_rewire_obuft.v" );
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}
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}
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+
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+ // Force 'keep' attribute on original IO BUF cells instantiated at RTL.
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+ // (ex: EDA-3307 where one I_BUF is removed by optimizer because input is not used)
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+ //
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+ void set_iobuf_keep_attribute ()
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+ {
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+ for (auto & modules : _design->selected_modules ()) {
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+
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+ for (auto & cell : modules->selected_cells ()) {
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+
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+ if (cell->type == RTLIL::escape_id (" I_BUF" )) {
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+ cell->set_bool_attribute (ID::keep);
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+ continue ;
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+ }
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+ if (cell->type == RTLIL::escape_id (" I_BUF_DS" )) {
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+ cell->set_bool_attribute (ID::keep);
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+ continue ;
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+ }
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+ if (cell->type == RTLIL::escape_id (" O_BUF" )) {
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+ cell->set_bool_attribute (ID::keep);
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+ continue ;
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+ }
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+ if (cell->type == RTLIL::escape_id (" O_BUF_DS" )) {
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+ cell->set_bool_attribute (ID::keep);
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+ continue ;
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+ }
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+ if (cell->type == RTLIL::escape_id (" O_BUFT" )) {
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+ cell->set_bool_attribute (ID::keep);
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+ continue ;
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+ }
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+ if (cell->type == RTLIL::escape_id (" O_BUFT_DS" )) {
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+ cell->set_bool_attribute (ID::keep);
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+ continue ;
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+ }
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+ }
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+ }
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+ }
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+
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// Map the $TBUF cells into OBUFT equivalent.
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//
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void map_obuft (RTLIL::Module* top_module)
@@ -8491,6 +8529,10 @@ void collect_clocks (RTLIL::Module* module,
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remove_print_cell ();
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illegal_clk_connection ();
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+ // set keep attribute on original IO buf cells
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+ //
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+ set_iobuf_keep_attribute ();
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+
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transform (nobram /* bmuxmap */ ); // no "$bmux" mapping in bram state
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#if 1
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