diff --git a/src/synth_rapidsilicon.cc b/src/synth_rapidsilicon.cc
index b91978a1..235e814f 100644
--- a/src/synth_rapidsilicon.cc
+++ b/src/synth_rapidsilicon.cc
@@ -7931,6 +7931,20 @@ void collect_clocks (RTLIL::Module* module,
        register_rule("O_DELAY", "DLY_ADJ", "f2g_trx_dly_adj", 0, all_rules);
        register_rule("O_DELAY", "DLY_INCDEC", "f2g_trx_dly_inc", 0, all_rules);
        register_rule("O_DELAY", "DLY_TAP_VALUE", "f2g_trx_dly_tap", 0, all_rules);
+
+#if 1
+
+       // Data signals
+       //
+       register_rule("O_BUF", "I", "f2g_tx_out", 0, all_rules);
+       register_rule("O_BUFT", "I", "f2g_tx_out", 0, all_rules);
+       register_rule("O_BUF_DS", "I", "f2g_tx_out", 0, all_rules);
+       register_rule("O_BUFT_DS", "I", "f2g_tx_out", 0, all_rules);
+       register_rule("O_DELAY", "I", "f2g_tx_out", 0, all_rules);
+       register_rule("O_DDR", "D", "f2g_tx_out", 0, all_rules);
+       register_rule("O_SERDES", "D", "f2g_tx_out", 0, all_rules);
+#endif
+
 #endif
 
        register_rule("I_DDR", "R", "f2g_trx_reset_n", 0, all_rules);
@@ -8055,8 +8069,9 @@ void collect_clocks (RTLIL::Module* module,
 
         for (auto cell : top_module->cells()) {
 
-           if (cell->type.in(ID(I_BUF_DS), ID(O_BUF_DS), ID(O_BUFT_DS), ID(O_SERDES), ID(I_SERDES),
-                            ID(BOOT_CLOCK), ID(O_DELAY), ID(I_DELAY), ID(O_SERDES_CLK), ID(PLL))) {
+           if (cell->type.in(ID(I_BUF_DS), ID(O_BUF_DS), ID(O_BUFT_DS), ID(O_SERDES), 
+                             ID(I_SERDES), ID(BOOT_CLOCK), ID(O_DELAY), ID(I_DELAY), 
+                             ID(O_BUF), ID(O_BUFT), ID(O_DDR))) {
 
 #if 0
              log("Collect Cell %s\n", (cell->type).c_str());