diff --git a/genesis3/FPGA_PRIMITIVES_MODELS b/genesis3/FPGA_PRIMITIVES_MODELS
index c3b0e742..e6466dbc 160000
--- a/genesis3/FPGA_PRIMITIVES_MODELS
+++ b/genesis3/FPGA_PRIMITIVES_MODELS
@@ -1 +1 @@
-Subproject commit c3b0e742d194e31bd56d20be4640268b02990197
+Subproject commit e6466dbc19bc2c318a9530e00f3c19e10719b0cc
diff --git a/src/synth_rapidsilicon.cc b/src/synth_rapidsilicon.cc
index 6c0f513a..d5710d1e 100644
--- a/src/synth_rapidsilicon.cc
+++ b/src/synth_rapidsilicon.cc
@@ -7880,7 +7880,7 @@ void collect_clocks (RTLIL::Module* module,
         // WARNING; we may need to handle case where 'keep' attribute is on
         // the I_BUF/O_BUF so that we cannot remove them.
         //
-#if 0
+#if 1
         remove_io_buffers(top_module);
 
         // Bypass the assigns by replacing LHs by RHS. Assigns will be