From 95d0ec35e65d1369d628c725d4cc7468cf7b8401 Mon Sep 17 00:00:00 2001
From: Ayyaz Ahmed <ayyazmayo@gmail.com>
Date: Tue, 15 Oct 2024 11:55:27 +0500
Subject: [PATCH] Revert EDA-3292 fix, effecting CLK_BUF inference

---
 src/synth_rapidsilicon.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/synth_rapidsilicon.cc b/src/synth_rapidsilicon.cc
index d5710d1e..6c0f513a 100644
--- a/src/synth_rapidsilicon.cc
+++ b/src/synth_rapidsilicon.cc
@@ -7880,7 +7880,7 @@ void collect_clocks (RTLIL::Module* module,
         // WARNING; we may need to handle case where 'keep' attribute is on
         // the I_BUF/O_BUF so that we cannot remove them.
         //
-#if 1
+#if 0
         remove_io_buffers(top_module);
 
         // Bypass the assigns by replacing LHs by RHS. Assigns will be