XG mobile dock lite - DP width

[gopalsr83]

@osy, first off, thank you for your fantastic work on the open source XG Mobile dock project.

I recently built the Lite version through JLCPCB, following the instructions on GitHub. The board works, but I’m only seeing PCIe 1.0 speeds when connecting it to my ROG Ally. I used a low-end Frontech GT740 (PCIe 3.0 x16 capable) for testing - not the best GPU, but it was the most accessible option. It’s possible a higher-quality card might negotiate higher link speeds.

As someone new to electronics and PCB design, I’ve been exploring your PCB design and schematic and had a question about the PCIe differential pair setup:

In the PCB editor under Board Setup > Net Classes, the DP width is set to 0.205486mm for PCIe signals. However, when I use JLCPCB's impedance calculator for a coplanar differential pair (with 85Ω target and the JLC0416H-7628 stackup), I get a recommended width of 0.1575mm. The 0.205mm value seems to align more with non-coplanar calculations.

Could you shed some light on this choice? I'm trying to better understand the rationale.

Thanks again for sharing your work!

[osy]

Originally I did not ground pour so it's non-coplaner and at some point I added a ground pour and forgot to recalculate it. However, the boards I got worked fine so I didn't change the value. If you look at the 6-layer version of the non-lite board you can see it's calculated with proper co-planer values.

The rounding is due to me using mils on the jlc tool and manually converting it to mm. I noticed that jlc rounds to nearest .001 and I thought it doesn't hurt to have more precision.

Also fyi for co-planer the trace to copper is 0.1mm

[gopalsr83]

Thanks for the explanation.