Check CORETYPE on cosmo

Check to make sure the core type is correct when sequencing. We have
an outstanding bug on v1 that prevenets `CPU_PRESENT` from working.

Author: labbott

drv/cosmo-seq-server/src/main.rs

@@ -69,7 +69,15 @@ enum Trace {
         seq_state: Result<fmc_periph::A0Sm, u8>,
     },
     PowerDownError(drv_cpu_seq_api::SeqError),
-
+    Coretype {
+        coretype0: bool,
+        coretype1: bool,
+        coretype2: bool,
+        sp5r1: bool,
+        sp5r2: bool,
+        sp5r3: bool,
+        sp5r4: bool,
+    },
     #[count(skip)]
     None,
 }
@@ -101,6 +109,25 @@ const SP_TO_FPGA2_SYSTEM_RESET_L: sys_api::PinSet = sys_api::Port::A.pin(5);
 // to use that pin for FMC).
 const SP_TO_IGN_TRGT_FPGA_FAULT_L: Option<sys_api::PinSet> = None;
 
+const SP5_TO_SP_PRESENT_L: sys_api::PinSet = sys_api::Port::C.pin(13);
+
+const SP5_TO_SP_SP5R1: sys_api::PinSet = sys_api::Port::I.pin(4);
+const SP5_TO_SP_SP5R2: sys_api::PinSet = sys_api::Port::H.pin(15);
+const SP5_TO_SP_SP5R3: sys_api::PinSet = sys_api::Port::F.pin(3);
+const SP5_TO_SP_SP5R4: sys_api::PinSet = sys_api::Port::F.pin(4);
+
+const SP5_TO_SP_CORETYPE0: sys_api::PinSet = sys_api::Port::I.pin(5);
+const SP5_TO_SP_CORETYPE1: sys_api::PinSet = sys_api::Port::I.pin(10);
+const SP5_TO_SP_CORETYPE2: sys_api::PinSet = sys_api::Port::I.pin(11);
+
+// All of these are externally pulled to V3P3_SP5_A1
+const CORETYPE_PULL: sys_api::Pull = sys_api::Pull::None;
+const CPU_PRESENT_L_PULL: sys_api::Pull = sys_api::Pull::None;
+const SP5R1_PULL: sys_api::Pull = sys_api::Pull::None;
+const SP5R2_PULL: sys_api::Pull = sys_api::Pull::None;
+const SP5R3_PULL: sys_api::Pull = sys_api::Pull::None;
+const SP5R4_PULL: sys_api::Pull = sys_api::Pull::None;
+
 ////////////////////////////////////////////////////////////////////////////////
 
 /// Helper type which includes both sequencer and NIC state machine states
@@ -181,6 +208,16 @@ fn init() -> Result<ServerImpl, SeqError> {
     );
     sys.gpio_reset(SP_CHASSIS_STATUS_LED);
 
+    // Set all of the presence-related pins to be inputs
+    sys.gpio_configure_input(SP5_TO_SP_CORETYPE0, CORETYPE_PULL);
+    sys.gpio_configure_input(SP5_TO_SP_CORETYPE1, CORETYPE_PULL);
+    sys.gpio_configure_input(SP5_TO_SP_CORETYPE2, CORETYPE_PULL);
+    sys.gpio_configure_input(SP5_TO_SP_PRESENT_L, CPU_PRESENT_L_PULL);
+    sys.gpio_configure_input(SP5_TO_SP_SP5R1, SP5R1_PULL);
+    sys.gpio_configure_input(SP5_TO_SP_SP5R2, SP5R2_PULL);
+    sys.gpio_configure_input(SP5_TO_SP_SP5R3, SP5R3_PULL);
+    sys.gpio_configure_input(SP5_TO_SP_SP5R4, SP5R4_PULL);
+
     let spi_front = drv_spi_api::Spi::from(SPI_FRONT.get_task_id());
     let aux = drv_auxflash_api::AuxFlash::from(AUXFLASH.get_task_id());
 
@@ -397,6 +434,11 @@ impl ServerImpl {
                         Ok(A0Sm::Faulted) | Err(_) => {
                             break;
                         }
+                        Ok(A0Sm::EnableGrpA) => {
+                            // We have an outstanding issue on v1 hardware-cosmo#658
+                            // that prevents us from checking `CPU_PRESENT` at
+                            // `A0Sm::ENABLE_GRP_A` time
+                        }
                         _ => (),
                     }
                     hl::sleep_for(10);
@@ -414,6 +456,46 @@ impl ServerImpl {
                     return Err(CpuSeqError::A0Timeout);
                 }
 
+                let coretype0 = self.sys.gpio_read(SP5_TO_SP_CORETYPE0) != 0;
+                let coretype1 = self.sys.gpio_read(SP5_TO_SP_CORETYPE1) != 0;
+                let coretype2 = self.sys.gpio_read(SP5_TO_SP_CORETYPE2) != 0;
+                let sp5r1 = self.sys.gpio_read(SP5_TO_SP_SP5R1) != 0;
+                let sp5r2 = self.sys.gpio_read(SP5_TO_SP_SP5R2) != 0;
+                let sp5r3 = self.sys.gpio_read(SP5_TO_SP_SP5R3) != 0;
+                let sp5r4 = self.sys.gpio_read(SP5_TO_SP_SP5R4) != 0;
+
+                ringbuf_entry!(Trace::Coretype {
+                    coretype0,
+                    coretype1,
+                    coretype2,
+                    sp5r1,
+                    sp5r2,
+                    sp5r3,
+                    sp5r4
+                });
+
+                // From sp5-mobo-guide-56870_1.1.pdf table 72
+                match (coretype0, coretype1, coretype2) {
+                    // These correspond to Type-2 and Type-3
+                    (true, false, true) | (true, false, false) => (),
+                    // Reject all other combos and return to A0
+                    _ => {
+                        self.seq.power_ctrl.modify(|m| m.set_a0_en(false));
+                        return Err(CpuSeqError::UnrecognizedCPU);
+                    }
+                };
+
+                // From sp5-mobo-guide-56870_1.1.pdf table 73
+                match (sp5r1, sp5r2, sp5r3, sp5r4) {
+                    // There is only combo we accept here
+                    (true, false, false, false) => (),
+                    // Reject all other combos and return to A0
+                    _ => {
+                        self.seq.power_ctrl.modify(|m| m.set_a0_en(false));
+                        return Err(CpuSeqError::UnrecognizedCPU);
+                    }
+                };
+
                 // Flip the host flash mux so the CPU can read from it
                 // (this is secretly infallible on Cosmo, so we can unwrap it)
                 self.hf.set_mux(drv_hf_api::HfMuxState::HostCPU).unwrap();