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qsys_mem_map.h
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#ifndef _ALTERA_QSYS_MEM_MAP_H_
#define _ALTERA_QSYS_MEM_MAP_H_
/*
* This file was automatically generated by the swinfo2header utility.
*
* Created from SOPC Builder system 'kyogenrv_fpga' in
* file 'C:\RISCV\kyogenrv\fpga/kyogenrv_fpga.swinfo'.
*/
/*
* This file contains macros for module 'KyogenRV_0' and devices
* connected to the following master:
* avalon_data_master
* This master belong to master group 'KyogenRV_0_avalon_data_master'
*
* Do not include this header file and another header file created for a
* different module or master group at the same time.
* Doing so may result in duplicate macro names.
* Instead, use the system header file which has macros with unique names.
*/
/*
* Macros for device 'onchip_memory2_0', class 'altera_avalon_onchip_memory2'
* The macros are prefixed with 'ONCHIP_MEMORY2_0_'.
* The prefix is the slave descriptor.
*/
#define ONCHIP_MEMORY2_0_COMPONENT_TYPE altera_avalon_onchip_memory2
#define ONCHIP_MEMORY2_0_COMPONENT_NAME onchip_memory2_0
#define ONCHIP_MEMORY2_0_BASE 0x0
#define ONCHIP_MEMORY2_0_SPAN 36864
#define ONCHIP_MEMORY2_0_END 0x8fff
#define ONCHIP_MEMORY2_0_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
#define ONCHIP_MEMORY2_0_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
#define ONCHIP_MEMORY2_0_CONTENTS_INFO ""
#define ONCHIP_MEMORY2_0_DUAL_PORT 0
#define ONCHIP_MEMORY2_0_GUI_RAM_BLOCK_TYPE AUTO
#define ONCHIP_MEMORY2_0_INIT_CONTENTS_FILE blinker_intel
#define ONCHIP_MEMORY2_0_INIT_MEM_CONTENT 1
#define ONCHIP_MEMORY2_0_INSTANCE_ID NONE
#define ONCHIP_MEMORY2_0_NON_DEFAULT_INIT_FILE_ENABLED 1
#define ONCHIP_MEMORY2_0_RAM_BLOCK_TYPE AUTO
#define ONCHIP_MEMORY2_0_READ_DURING_WRITE_MODE DONT_CARE
#define ONCHIP_MEMORY2_0_SINGLE_CLOCK_OP 1
#define ONCHIP_MEMORY2_0_SIZE_MULTIPLE 1
#define ONCHIP_MEMORY2_0_SIZE_VALUE 36864
#define ONCHIP_MEMORY2_0_WRITABLE 1
#define ONCHIP_MEMORY2_0_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR
#define ONCHIP_MEMORY2_0_MEMORY_INFO_GENERATE_DAT_SYM 1
#define ONCHIP_MEMORY2_0_MEMORY_INFO_GENERATE_HEX 1
#define ONCHIP_MEMORY2_0_MEMORY_INFO_HAS_BYTE_LANE 0
#define ONCHIP_MEMORY2_0_MEMORY_INFO_HEX_INSTALL_DIR QPF_DIR
#define ONCHIP_MEMORY2_0_MEMORY_INFO_MEM_INIT_DATA_WIDTH 32
#define ONCHIP_MEMORY2_0_MEMORY_INFO_MEM_INIT_FILENAME blinker_intel
/*
* Macros for device 'i2c_0', class 'altera_avalon_i2c'
* The macros are prefixed with 'I2C_0_'.
* The prefix is the slave descriptor.
*/
#define I2C_0_COMPONENT_TYPE altera_avalon_i2c
#define I2C_0_COMPONENT_NAME i2c_0
#define I2C_0_BASE 0x10000
#define I2C_0_SPAN 64
#define I2C_0_END 0x1003f
#define I2C_0_FIFO_DEPTH 4
#define I2C_0_FREQ 70000000
#define I2C_0_USE_AV_ST 0
/*
* Macros for device 'uart_0', class 'altera_avalon_uart'
* The macros are prefixed with 'UART_0_'.
* The prefix is the slave descriptor.
*/
#define UART_0_COMPONENT_TYPE altera_avalon_uart
#define UART_0_COMPONENT_NAME uart_0
#define UART_0_BASE 0x10040
#define UART_0_SPAN 32
#define UART_0_END 0x1005f
#define UART_0_BAUD 115200
#define UART_0_DATA_BITS 8
#define UART_0_FIXED_BAUD 1
#define UART_0_FREQ 70000000
#define UART_0_PARITY 'N'
#define UART_0_SIM_CHAR_STREAM ""
#define UART_0_SIM_TRUE_BAUD 0
#define UART_0_STOP_BITS 1
#define UART_0_SYNC_REG_DEPTH 2
#define UART_0_USE_CTS_RTS 0
#define UART_0_USE_EOP_REGISTER 0
/*
* Macros for device 'msgdma_0_csr', class 'altera_msgdma'
* The macros are prefixed with 'MSGDMA_0_CSR_'.
* The prefix is the slave descriptor.
*/
#define MSGDMA_0_CSR_COMPONENT_TYPE altera_msgdma
#define MSGDMA_0_CSR_COMPONENT_NAME msgdma_0
#define MSGDMA_0_CSR_BASE 0x10060
#define MSGDMA_0_CSR_SPAN 32
#define MSGDMA_0_CSR_END 0x1007f
#define MSGDMA_0_CSR_BURST_ENABLE 0
#define MSGDMA_0_CSR_BURST_WRAPPING_SUPPORT 0
#define MSGDMA_0_CSR_CHANNEL_ENABLE 0
#define MSGDMA_0_CSR_CHANNEL_ENABLE_DERIVED 0
#define MSGDMA_0_CSR_CHANNEL_WIDTH 8
#define MSGDMA_0_CSR_DATA_FIFO_DEPTH 32
#define MSGDMA_0_CSR_DATA_WIDTH 32
#define MSGDMA_0_CSR_DESCRIPTOR_FIFO_DEPTH 128
#define MSGDMA_0_CSR_DMA_MODE 2
#define MSGDMA_0_CSR_ENHANCED_FEATURES 0
#define MSGDMA_0_CSR_ERROR_ENABLE 0
#define MSGDMA_0_CSR_ERROR_ENABLE_DERIVED 0
#define MSGDMA_0_CSR_ERROR_WIDTH 8
#define MSGDMA_0_CSR_MAX_BURST_COUNT 2
#define MSGDMA_0_CSR_MAX_BYTE 1024
#define MSGDMA_0_CSR_MAX_STRIDE 1
#define MSGDMA_0_CSR_PACKET_ENABLE 0
#define MSGDMA_0_CSR_PACKET_ENABLE_DERIVED 0
#define MSGDMA_0_CSR_PREFETCHER_ENABLE 0
#define MSGDMA_0_CSR_PROGRAMMABLE_BURST_ENABLE 0
#define MSGDMA_0_CSR_RESPONSE_PORT 2
#define MSGDMA_0_CSR_STRIDE_ENABLE 0
#define MSGDMA_0_CSR_STRIDE_ENABLE_DERIVED 0
#define MSGDMA_0_CSR_TRANSFER_TYPE Aligned Accesses
/*
* Macros for device 'pio_0', class 'altera_avalon_pio'
* The macros are prefixed with 'PIO_0_'.
* The prefix is the slave descriptor.
*/
#define PIO_0_COMPONENT_TYPE altera_avalon_pio
#define PIO_0_COMPONENT_NAME pio_0
#define PIO_0_BASE 0x10080
#define PIO_0_SPAN 16
#define PIO_0_END 0x1008f
#define PIO_0_BIT_CLEARING_EDGE_REGISTER 0
#define PIO_0_BIT_MODIFYING_OUTPUT_REGISTER 0
#define PIO_0_CAPTURE 0
#define PIO_0_DATA_WIDTH 8
#define PIO_0_DO_TEST_BENCH_WIRING 0
#define PIO_0_DRIVEN_SIM_VALUE 0
#define PIO_0_EDGE_TYPE NONE
#define PIO_0_FREQ 70000000
#define PIO_0_HAS_IN 0
#define PIO_0_HAS_OUT 1
#define PIO_0_HAS_TRI 0
#define PIO_0_IRQ_TYPE NONE
#define PIO_0_RESET_VALUE 0
/*
* Macros for device 'msgdma_0_descriptor_slave', class 'altera_msgdma'
* The macros are prefixed with 'MSGDMA_0_DESCRIPTOR_SLAVE_'.
* The prefix is the slave descriptor.
*/
#define MSGDMA_0_DESCRIPTOR_SLAVE_COMPONENT_TYPE altera_msgdma
#define MSGDMA_0_DESCRIPTOR_SLAVE_COMPONENT_NAME msgdma_0
#define MSGDMA_0_DESCRIPTOR_SLAVE_BASE 0x10090
#define MSGDMA_0_DESCRIPTOR_SLAVE_SPAN 16
#define MSGDMA_0_DESCRIPTOR_SLAVE_END 0x1009f
#define MSGDMA_0_DESCRIPTOR_SLAVE_BURST_ENABLE 0
#define MSGDMA_0_DESCRIPTOR_SLAVE_BURST_WRAPPING_SUPPORT 0
#define MSGDMA_0_DESCRIPTOR_SLAVE_CHANNEL_ENABLE 0
#define MSGDMA_0_DESCRIPTOR_SLAVE_CHANNEL_ENABLE_DERIVED 0
#define MSGDMA_0_DESCRIPTOR_SLAVE_CHANNEL_WIDTH 8
#define MSGDMA_0_DESCRIPTOR_SLAVE_DATA_FIFO_DEPTH 32
#define MSGDMA_0_DESCRIPTOR_SLAVE_DATA_WIDTH 32
#define MSGDMA_0_DESCRIPTOR_SLAVE_DESCRIPTOR_FIFO_DEPTH 128
#define MSGDMA_0_DESCRIPTOR_SLAVE_DMA_MODE 2
#define MSGDMA_0_DESCRIPTOR_SLAVE_ENHANCED_FEATURES 0
#define MSGDMA_0_DESCRIPTOR_SLAVE_ERROR_ENABLE 0
#define MSGDMA_0_DESCRIPTOR_SLAVE_ERROR_ENABLE_DERIVED 0
#define MSGDMA_0_DESCRIPTOR_SLAVE_ERROR_WIDTH 8
#define MSGDMA_0_DESCRIPTOR_SLAVE_MAX_BURST_COUNT 2
#define MSGDMA_0_DESCRIPTOR_SLAVE_MAX_BYTE 1024
#define MSGDMA_0_DESCRIPTOR_SLAVE_MAX_STRIDE 1
#define MSGDMA_0_DESCRIPTOR_SLAVE_PACKET_ENABLE 0
#define MSGDMA_0_DESCRIPTOR_SLAVE_PACKET_ENABLE_DERIVED 0
#define MSGDMA_0_DESCRIPTOR_SLAVE_PREFETCHER_ENABLE 0
#define MSGDMA_0_DESCRIPTOR_SLAVE_PROGRAMMABLE_BURST_ENABLE 0
#define MSGDMA_0_DESCRIPTOR_SLAVE_RESPONSE_PORT 2
#define MSGDMA_0_DESCRIPTOR_SLAVE_STRIDE_ENABLE 0
#define MSGDMA_0_DESCRIPTOR_SLAVE_STRIDE_ENABLE_DERIVED 0
#define MSGDMA_0_DESCRIPTOR_SLAVE_TRANSFER_TYPE Aligned Accesses
/*
* Macros for device 'sdram_0', class 'altera_avalon_new_sdram_controller'
* The macros are prefixed with 'SDRAM_0_'.
* The prefix is the slave descriptor.
*/
#define SDRAM_0_COMPONENT_TYPE altera_avalon_new_sdram_controller
#define SDRAM_0_COMPONENT_NAME sdram_0
#define SDRAM_0_BASE 0x800000
#define SDRAM_0_SPAN 8388608
#define SDRAM_0_END 0xffffff
#define SDRAM_0_CAS_LATENCY 3
#define SDRAM_0_CONTENTS_INFO
#define SDRAM_0_INIT_NOP_DELAY 0.0
#define SDRAM_0_INIT_REFRESH_COMMANDS 2
#define SDRAM_0_IS_INITIALIZED 1
#define SDRAM_0_POWERUP_DELAY 100.0
#define SDRAM_0_REFRESH_PERIOD 7.8125
#define SDRAM_0_REGISTER_DATA_IN 1
#define SDRAM_0_SDRAM_ADDR_WIDTH 22
#define SDRAM_0_SDRAM_BANK_WIDTH 2
#define SDRAM_0_SDRAM_COL_WIDTH 8
#define SDRAM_0_SDRAM_DATA_WIDTH 16
#define SDRAM_0_SDRAM_NUM_BANKS 4
#define SDRAM_0_SDRAM_NUM_CHIPSELECTS 1
#define SDRAM_0_SDRAM_ROW_WIDTH 12
#define SDRAM_0_SHARED_DATA 0
#define SDRAM_0_SIM_MODEL_BASE 0
#define SDRAM_0_STARVATION_INDICATOR 0
#define SDRAM_0_TRISTATE_BRIDGE_SLAVE ""
#define SDRAM_0_T_AC 5.5
#define SDRAM_0_T_MRD 3
#define SDRAM_0_T_RCD 20.0
#define SDRAM_0_T_RFC 70.0
#define SDRAM_0_T_RP 20.0
#define SDRAM_0_T_WR 14.0
#define SDRAM_0_MEMORY_INFO_DAT_SYM_INSTALL_DIR SIM_DIR
#define SDRAM_0_MEMORY_INFO_GENERATE_DAT_SYM 1
#define SDRAM_0_MEMORY_INFO_MEM_INIT_DATA_WIDTH 16
#endif /* _ALTERA_QSYS_MEM_MAP_H_ */