As a convenience common multi-level optimizations setups could be defined

[pedrocr]

As a follow-up to #1 it would probably be nice to have a few convenience macros that encode common performance ladders used in several places. For example for SIMD there is a progression in features on x86 and probably a similar one on ARM. It would be nice if there was a convenience `#[runtime_target_simd_features]' or similar that would encode a reasonable performance ladder for both Intel and ARM so this doesn't need to be replicated inconsistently in a bunch of projects.

[parched]

I agree, do you have a suggestion what the x86 ones might be? I imagine we don't want the full ladder as that would mean a lot of code duplication?

[pedrocr]

Considering this:

https://en.wikipedia.org/wiki/List_of_Intel_CPU_microarchitectures

the progression seems to be the following:

• Just SSE up to SSSE3 (I believe all x86_64 cpus have at least this)
• SSE4 (introduced in Core)
• SSE4.2 (introduced in Nehalem and Silvermont for Atom)
• AVX (introduced in Sandy Bridge)
• AVX2 (introduced in Haswell)
• AVX512 (introduced in Skylake)

Having 6 levels in total doesn't sound too much if this is just used in hot paths. A cool optimization would be if somehow it were possible to disable levels that generate the same code but that's probably only possible with deeper links into the LLVM IR.